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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-04-09 13:50:41 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-04-16 13:40:28 +0200 |
| commit | 246e232437e5a045792aee95b2f9c7718516596c (patch) | |
| tree | 3703cc504972545e7746ecf6865cc0a17cc63439 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 279ebbcae5a1298433c1b4f9425c89897d017cc0 (diff) | |
clk: renesas: r8a77980: Correct parent clock of PCIEC0
According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of
December 22, 2017, the parent clock of the PCIe module clock on R-Car
V3H is S2D2.
Fixes: ce15783c510a9905 ("clk: renesas: cpg-mssr: add R8A77980 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions