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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-03-29 11:03:00 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-04-16 13:39:51 +0200 |
| commit | 279ebbcae5a1298433c1b4f9425c89897d017cc0 (patch) | |
| tree | adcf64974d36ac5011d1784b878d09ea7a64899f /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 0873305e68ac2a4665f1f3d27bb0b98a4312e5bd (diff) | |
clk: renesas: r8a7794: Fix LB clock divider
The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.
On R-Car E2, the LB clock divider is fixed to 24. Hence model the clock
as a fixed factor clock instead.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions