genirq: Generic chip: Handle separate mask registers

There are cases where all irq_chip_type instances have separate mask
registers, making a shared mask register cache unsuitable for the
purpose.

Introduce a new flag IRQ_GC_MASK_CACHE_PER_TYPE. If set, point the per
chip mask pointer to the per chip private mask cache instead.

[ tglx: Simplified code, renamed flag and massaged changelog ]

Signed-off-by: Gerlando Falauto <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Joey Oravec <[email protected]>
Cc: Lennert Buytenhek <[email protected]>
Cc: Russell King - ARM Linux <[email protected]>
Cc: Jason Gunthorpe <[email protected]>
Cc: Holger Brunck <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Acked-by: Grant Likely <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: [email protected]
Cc: Rob Herring <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Gregory Clement <[email protected]>
Cc: Simon Guinot <[email protected]>
Cc: [email protected]
Cc: Thomas Petazzoni <[email protected]>
Cc: Jean-Francois Moine <[email protected]>
Cc: Nicolas Pitre <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Maxime Ripard <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Thomas Gleixner <[email protected]>

0 files changed, 0 insertions, 0 deletions