genirq: Generic chip: Add support for per chip type mask cache

Today the same interrupt mask cache (stored within struct irq_chip_generic)
is shared between all the irq_chip_type instances. As there are instances
where each irq_chip_type uses a distinct mask register (as it is the case
for Orion SoCs), sharing a single mask cache may be incorrect.
So add a distinct pointer for each irq_chip_type, which for now
points to the original mask register within irq_chip_generic.
So no functional changes here.

[ tglx: Minor cosmetic tweaks ]

Reported-by: Joey Oravec <[email protected]>
Signed-off-by: Simon Guinot <[email protected]>
Signed-off-by: Holger Brunck <[email protected]>
Signed-off-by: Gerlando Falauto <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Lennert Buytenhek <[email protected]>
Cc: Russell King - ARM Linux <[email protected]>
Cc: Jason Gunthorpe <[email protected]>
Cc: Holger Brunck <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Acked-by: Grant Likely <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: [email protected]
Cc: Rob Herring <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Gregory Clement <[email protected]>
Cc: Simon Guinot <[email protected]>
Cc: [email protected]
Cc: Thomas Petazzoni <[email protected]>
Cc: Jean-Francois Moine <[email protected]>
Cc: Nicolas Pitre <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Maxime Ripard <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Thomas Gleixner <[email protected]>

0 files changed, 0 insertions, 0 deletions