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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-07-19 15:38:09 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-26 14:10:59 +0200 |
| commit | 0b256c403d4082bafc681143913442288010277c (patch) | |
| tree | 1814e739e7b1107b9e688bde8bcfb5f9c5ef3c76 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 2734d6c1b1a089fb593ef6a23d4b70903526fe0c (diff) | |
dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock
Add P0_DIV2 core clock required for CANFD module. CANFD core clock is
sourced from P0_DIV2 referenced from HW manual Rev.0.50.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719143811.2135-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions