diff options
| author | Lad Prabhakar <[email protected]> | 2021-07-19 15:38:09 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2021-07-26 14:10:59 +0200 |
| commit | 0b256c403d4082bafc681143913442288010277c (patch) | |
| tree | 1814e739e7b1107b9e688bde8bcfb5f9c5ef3c76 | |
| parent | 2734d6c1b1a089fb593ef6a23d4b70903526fe0c (diff) | |
dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock
Add P0_DIV2 core clock required for CANFD module. CANFD core clock is
sourced from P0_DIV2 referenced from HW manual Rev.0.50.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
| -rw-r--r-- | include/dt-bindings/clock/r9a07g044-cpg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h index 0728ad07ff7a..0bb17ff1a01a 100644 --- a/include/dt-bindings/clock/r9a07g044-cpg.h +++ b/include/dt-bindings/clock/r9a07g044-cpg.h @@ -30,6 +30,7 @@ #define R9A07G044_CLK_P2 19 #define R9A07G044_CLK_AT 20 #define R9A07G044_OSCCLK 21 +#define R9A07G044_CLK_P0_DIV2 22 /* R9A07G044 Module Clocks */ #define R9A07G044_CA55_SCLK 0 |