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| author | Madhav Chauhan <[email protected]> | 2018-10-15 17:28:01 +0300 |
|---|---|---|
| committer | Jani Nikula <[email protected]> | 2018-10-22 15:14:19 +0300 |
| commit | 70f4f502c47e9c541b0ae329440a7fe809cc5211 (patch) | |
| tree | ead75eaf468ae52d67f8b07f74bca8a92e4cc839 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 49edbd49786ee32b24f43efd383c9e97528cc4aa (diff) | |
drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers
This patch select input PIPE for DSI, data lanes width,
enable port sync mode and wait for DSI link to become ready.
v2 by Jani:
- Use MISSING_CASE with fallthrough instead of DRM_ERROR
- minor stylistic changes
Signed-off-by: Madhav Chauhan <[email protected]>
Signed-off-by: Jani Nikula <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/080320dc9a9e321dbe73567c6a7aa1dcff0f21c2.1539613303.git.jani.nikula@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions