diff options
| author | Madhav Chauhan <[email protected]> | 2018-10-15 17:28:00 +0300 |
|---|---|---|
| committer | Jani Nikula <[email protected]> | 2018-10-22 15:14:03 +0300 |
| commit | 49edbd49786ee32b24f43efd383c9e97528cc4aa (patch) | |
| tree | 6e99afc5753e68882f714eae6f4a3817d1d87d95 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 9128b10249543200fbd26758beab2e7dd93addfc (diff) | |
drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers
This patch defines TRANS_DDI_FUNC_CTL and TRANS_DDI_FUNC_CTL2
registers and their bitfields for DSI. These registers are used
for enabling port sync mode, input pipe select, data lane width
configuration etc.
v2: Changes:
- Remove redundant extra line
- Correct some of bitfield definition
v3 by Jani:
- Move DSI transcoder offsets to GEN11_FEATURES
Signed-off-by: Madhav Chauhan <[email protected]>
Signed-off-by: Jani Nikula <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/6b2d87db82660320be10e423742cbf5a31e18037.1539613303.git.jani.nikula@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions