staging: iio: resolver: ad2s1210: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.  As the tx[] an rx[] buffers are only used
in the same SPI exchanges, we should be safe with them on the same cacheline.
Hence only mark the first one __aligned(IIO_DMA_MINALIGN).

Signed-off-by: Jonathan Cameron <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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