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authorYazen Ghannam <[email protected]>2019-08-22 00:00:02 +0000
committerBorislav Petkov <[email protected]>2019-08-23 16:09:52 +0200
commit81f5090db843be897414418c24fe472fa6e082b6 (patch)
tree5f8ff7ca5c5d5f8c7ad311caa452f446a3b19a00 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py
parent7574729e91468d568cc198de438feb35ef04f41a (diff)
EDAC/amd64: Support asymmetric dual-rank DIMMs
Future AMD systems will support asymmetric dual-rank DIMMs. These are DIMMs where the ranks are of different sizes. The even rank will use the Primary Even Chip Select registers and the odd rank will use the Secondary Odd Chip Select registers. Recognize if a Secondary Odd Chip Select is being used. Use the Secondary Odd Address Mask when calculating the chip select size. [ bp: move csrow_sec_enabled() to the header, fix CS_ODD define and tone-down the capitalized words spelling. ] Signed-off-by: Yazen Ghannam <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> Cc: "[email protected]" <[email protected]> Cc: James Morse <[email protected]> Cc: Mauro Carvalho Chehab <[email protected]> Cc: Tony Luck <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
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