diff options
| author | Yazen Ghannam <[email protected]> | 2019-08-22 00:00:01 +0000 |
|---|---|---|
| committer | Borislav Petkov <[email protected]> | 2019-08-23 12:55:05 +0200 |
| commit | 7574729e91468d568cc198de438feb35ef04f41a (patch) | |
| tree | ecdf3925e06343e3c7385f13c358858b664da548 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
| parent | 8a2eaab7daf03b23ac902481218034ae2fae5e16 (diff) | |
EDAC/amd64: Cache secondary Chip Select registers
AMD Family 17h systems have a set of secondary Chip Select Base
Addresses and Address Masks. These do not represent unique Chip
Selects, rather they are used in conjunction with the primary
Chip Select registers in certain cases.
Cache these secondary Chip Select registers for future use.
Signed-off-by: Yazen Ghannam <[email protected]>
Signed-off-by: Borislav Petkov <[email protected]>
Cc: "[email protected]" <[email protected]>
Cc: James Morse <[email protected]>
Cc: Mauro Carvalho Chehab <[email protected]>
Cc: Tony Luck <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
0 files changed, 0 insertions, 0 deletions