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authorConor Dooley <[email protected]>2023-01-04 18:05:14 +0000
committerPalmer Dabbelt <[email protected]>2023-02-14 19:24:06 -0800
commit991994509ee93f7698251e696b8e5591e01b7f68 (patch)
tree3994f6ba918ba48052854d20b0d9de6af394be4f /scripts/generate_rust_analyzer.py
parent7d2078310cbf0fa7fb4323d595fe093c418dcd37 (diff)
dt-bindings: riscv: add a capacity-dmips-mhz cpu property
Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") RISC-V has used the generic arch topology code, which provides for disparate CPU capacities. We never defined a binding to acquire this information from the DT though, so document the one already used by the generic arch topology code: "capacity-dmips-mhz". Signed-off-by: Conor Dooley <[email protected]> Reviewed-by: Ley Foon Tan <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
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