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authorConor Dooley <[email protected]>2023-01-04 18:05:14 +0000
committerPalmer Dabbelt <[email protected]>2023-02-14 19:24:06 -0800
commit991994509ee93f7698251e696b8e5591e01b7f68 (patch)
tree3994f6ba918ba48052854d20b0d9de6af394be4f
parent7d2078310cbf0fa7fb4323d595fe093c418dcd37 (diff)
dt-bindings: riscv: add a capacity-dmips-mhz cpu property
Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") RISC-V has used the generic arch topology code, which provides for disparate CPU capacities. We never defined a binding to acquire this information from the DT though, so document the one already used by the generic arch topology code: "capacity-dmips-mhz". Signed-off-by: Conor Dooley <[email protected]> Reviewed-by: Ley Foon Tan <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
-rw-r--r--Documentation/devicetree/bindings/riscv/cpus.yaml6
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index a2884e3113da..001931d526ec 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -114,6 +114,12 @@ properties:
List of phandles to idle state nodes supported
by this hart (see ./idle-states.yaml).
+ capacity-dmips-mhz:
+ description:
+ u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
+ DMIPS/MHz, relative to highest capacity-dmips-mhz
+ in the system.
+
required:
- riscv,isa
- interrupt-controller