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authorRadhakrishna Sripada <[email protected]>2023-12-07 14:10:25 -0800
committerRadhakrishna Sripada <[email protected]>2023-12-08 10:59:52 -0800
commit872ee9cc0219334486e19da20e56665e612fdcb7 (patch)
treedd1a059229a34520e60258819fb5115644a37b5a /scripts/generate_rust_analyzer.py
parent1103672fd6b8486c4cc1ab69623e9a080a00e022 (diff)
drm/i915/mtl: Rename the link_bit_rate to clock in C20 pll_state
With the cleanup of the misleading clock value to avoid extra calculations to convert between link_bit_rate and clock, use one standard "clock" field for the c20 pll which works with crtc_state->port_clock field. Cc: Clint Taylor <[email protected]> Cc: Mika Kahola <[email protected]> Signed-off-by: Radhakrishna Sripada <[email protected]> Reviewed-by: Mika Kahola <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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