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authorDamien Le Moal <[email protected]>2021-06-22 15:45:02 +0900
committerStephen Boyd <[email protected]>2021-06-30 11:34:36 -0700
commitfaa0e307948594b4379a86fff7fb2409067aed6f (patch)
treebf91ae414498d4bffc1092065a8aff1cdaeaba5b /scripts/gdb/linux/config.py
parent2cdee50eda9d87f4fabba3df00caa4cc873f30ab (diff)
clk: k210: Fix k210_clk_set_parent()
In k210_clk_set_parent(), add missing writel() call to update the mux register of a clock to change its parent. This also fixes a compilation warning with clang when compiling with W=1. Fixes: c6ca7616f7d5 ("clk: Add RISC-V Canaan Kendryte K210 clock driver") Cc: [email protected] Signed-off-by: Damien Le Moal <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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