diff options
| author | Biju Das <[email protected]> | 2022-08-02 11:15:34 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2022-08-22 09:46:03 +0200 |
| commit | 72a482dbaec4b9e4d54b81be6bdb8c016fd2f4bd (patch) | |
| tree | 84847dbad1e9774fa145e1d923746b406e4ef37f /net/lapb/lapb_timer.c | |
| parent | 13dec051c7f139eef345c55a60941843e72128f1 (diff) | |
arm64: dts: renesas: r9a07g043: Fix SCI{Rx,Tx} interrupt types
As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022),
the interrupt type of SCI{Rx,Tx} is edge triggered.
Signed-off-by: Biju Das <[email protected]>
Fixes: cf40c9689e5109bf ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'net/lapb/lapb_timer.c')
0 files changed, 0 insertions, 0 deletions