diff options
| author | Xingyu Wu <[email protected]> | 2023-07-13 19:38:56 +0800 |
|---|---|---|
| committer | Conor Dooley <[email protected]> | 2023-07-19 18:08:00 +0100 |
| commit | 9b3938c0b81e79e1c0e1a3e95be3e12efd8c771b (patch) | |
| tree | be1dd5142a92968b5756b99893f4f69ea145dc0d /lib/test_fortify/write_overflow-strncpy-src.c | |
| parent | 14b14a57e642e0dab9be4e9d0866fb2c4332f7c5 (diff) | |
dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.
Acked-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Diffstat (limited to 'lib/test_fortify/write_overflow-strncpy-src.c')
0 files changed, 0 insertions, 0 deletions