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| author | Doug Brown <doug@schmorgal.com> | 2024-05-19 12:19:30 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-06-04 14:08:09 +0200 |
| commit | 5208e7ced520a813b4f4774451fbac4e517e78b2 (patch) | |
| tree | 7e7a6e900c30d4c7d543f7775aacc857503381b1 /lib/crypto/mpi/mpi-internal.h | |
| parent | 2c94512055f362dd789e0f87b8566feeddec83c9 (diff) | |
serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level
The FIFO is 64 bytes, but the FCR is configured to fire the TX interrupt
when the FIFO is half empty (bit 3 = 0). Thus, we should only write 32
bytes when a TX interrupt occurs.
This fixes a problem observed on the PXA168 that dropped a bunch of TX
bytes during large transmissions.
Fixes: ab28f51c77cd ("serial: rewrite pxa2xx-uart to use 8250_core")
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20240519191929.122202-1-doug@schmorgal.com
Cc: stable <stable@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'lib/crypto/mpi/mpi-internal.h')
0 files changed, 0 insertions, 0 deletions