diff options
| author | Doug Brown <[email protected]> | 2024-05-19 12:19:30 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2024-06-04 14:08:09 +0200 |
| commit | 5208e7ced520a813b4f4774451fbac4e517e78b2 (patch) | |
| tree | 7e7a6e900c30d4c7d543f7775aacc857503381b1 | |
| parent | 2c94512055f362dd789e0f87b8566feeddec83c9 (diff) | |
serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level
The FIFO is 64 bytes, but the FCR is configured to fire the TX interrupt
when the FIFO is half empty (bit 3 = 0). Thus, we should only write 32
bytes when a TX interrupt occurs.
This fixes a problem observed on the PXA168 that dropped a bunch of TX
bytes during large transmissions.
Fixes: ab28f51c77cd ("serial: rewrite pxa2xx-uart to use 8250_core")
Signed-off-by: Doug Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Cc: stable <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
| -rw-r--r-- | drivers/tty/serial/8250/8250_pxa.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/tty/serial/8250/8250_pxa.c b/drivers/tty/serial/8250/8250_pxa.c index f1a51b00b1b9..ba96fa913e7f 100644 --- a/drivers/tty/serial/8250/8250_pxa.c +++ b/drivers/tty/serial/8250/8250_pxa.c @@ -125,6 +125,7 @@ static int serial_pxa_probe(struct platform_device *pdev) uart.port.iotype = UPIO_MEM32; uart.port.regshift = 2; uart.port.fifosize = 64; + uart.tx_loadsz = 32; uart.dl_write = serial_pxa_dl_write; ret = serial8250_register_8250_port(&uart); |