diff options
| author | Bhupesh Sharma <[email protected]> | 2022-03-03 02:00:41 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2022-03-09 08:53:29 -0600 |
| commit | 2dc63e768ce2fbf24cb49c858f549596bb30a0a0 (patch) | |
| tree | a834d89c6919cc7e912ef68a4afc505ef6f0d35c /include | |
| parent | b527358cb4cd58a8279c9062b0786f1fab628fdc (diff) | |
clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150
Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150.
Cc: Stephen Boyd <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/qcom,gcc-sm8150.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index 3e1a91876610..ae9c16410420 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -241,6 +241,8 @@ #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 /* GCC GDSCRs */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 #define USB30_PRIM_GDSC 4 #define USB30_SEC_GDSC 5 |