diff options
| author | Bhupesh Sharma <[email protected]> | 2022-03-03 02:00:41 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2022-03-09 08:53:29 -0600 |
| commit | 2dc63e768ce2fbf24cb49c858f549596bb30a0a0 (patch) | |
| tree | a834d89c6919cc7e912ef68a4afc505ef6f0d35c | |
| parent | b527358cb4cd58a8279c9062b0786f1fab628fdc (diff) | |
clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150
Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150.
Cc: Stephen Boyd <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | drivers/clk/qcom/gcc-sm8150.c | 20 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,gcc-sm8150.h | 2 |
2 files changed, 22 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index 245794485719..7e478dc2cefe 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -3448,6 +3448,24 @@ static struct clk_branch gcc_video_xo_clk = { }, }; +static struct gdsc pcie_0_gdsc = { + .gdscr = 0x6b004, + .pd = { + .name = "pcie_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR, +}; + +static struct gdsc pcie_1_gdsc = { + .gdscr = 0x8d004, + .pd = { + .name = "pcie_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR, +}; + static struct gdsc usb30_prim_gdsc = { .gdscr = 0xf004, .pd = { @@ -3714,6 +3732,8 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = { }; static struct gdsc *gcc_sm8150_gdscs[] = { + [PCIE_0_GDSC] = &pcie_0_gdsc, + [PCIE_1_GDSC] = &pcie_1_gdsc, [USB30_PRIM_GDSC] = &usb30_prim_gdsc, [USB30_SEC_GDSC] = &usb30_sec_gdsc, }; diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index 3e1a91876610..ae9c16410420 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -241,6 +241,8 @@ #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 /* GCC GDSCRs */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 #define USB30_PRIM_GDSC 4 #define USB30_SEC_GDSC 5 |