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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-07-07 16:47:32 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2022-08-01 15:15:33 -0500 |
| commit | 91a773f9986b5cb4d6a6610b0326ef7c472dd543 (patch) | |
| tree | 63ba1b05bdbc1688b09efbf6a20dee598817ff92 /drivers/pci/controller/dwc/pci-exynos.c | |
| parent | cd761378e62c2614a3e7a1a8e4ecf68503a2c877 (diff) | |
dt-bindings: PCI: qcom: Support additional MSI vectors
On Qualcomm platforms each group of 32 MSI vectors is routed to the
separate GIC interrupt. Document mapping of additional interrupts.
Link: https://lore.kernel.org/r/20220707134733.2436629-6-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pci-exynos.c')
0 files changed, 0 insertions, 0 deletions