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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-07-07 16:47:31 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2022-08-01 15:15:33 -0500 |
| commit | cd761378e62c2614a3e7a1a8e4ecf68503a2c877 (patch) | |
| tree | 241ce6311c910b6e509378250ce0041e6f3dd1f9 /drivers/pci/controller/dwc/pci-exynos.c | |
| parent | db388348acffe954656ec38440809ec770707417 (diff) | |
PCI: dwc: Handle MSIs routed to multiple GIC interrupts
On some Qualcomm platforms each group of 32 MSI vectors is routed to a
separate GIC interrupt. Implement support for such configurations by
parsing "msi0" ... "msiX" interrupts and attaching them to the chained
handler.
Note that if DT doesn't list an array of MSI interrupts and uses a single
"msi" IRQ, the driver will limit the number of supported MSI vectors to 32.
Link: https://lore.kernel.org/r/20220707134733.2436629-5-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Diffstat (limited to 'drivers/pci/controller/dwc/pci-exynos.c')
0 files changed, 0 insertions, 0 deletions