diff options
| author | Marek Vasut <marex@denx.de> | 2019-06-28 02:19:44 +0200 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2019-07-30 09:05:45 -0500 |
| commit | 2dbaa6a6dcf01b84bcf076a0e906dc7dacbd0a1d (patch) | |
| tree | 810ac9fd567f05b8a6016d2d0bf7c7a1cdc557f3 /drivers/gpu/drm/i915/gt/intel_ringbuffer.c | |
| parent | 325ec920eeb7b96b9cb490213bfdb03650c19d86 (diff) | |
ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA
Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew
to minimum (-420 ps), to improve signal integrity.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_ringbuffer.c')
0 files changed, 0 insertions, 0 deletions