diff options
| author | Marek Vasut <marex@denx.de> | 2019-06-28 02:19:44 +0200 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2019-07-30 09:05:45 -0500 |
| commit | 2dbaa6a6dcf01b84bcf076a0e906dc7dacbd0a1d (patch) | |
| tree | 810ac9fd567f05b8a6016d2d0bf7c7a1cdc557f3 | |
| parent | 325ec920eeb7b96b9cb490213bfdb03650c19d86 (diff) | |
ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA
Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew
to minimum (-420 ps), to improve signal integrity.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
| -rw-r--r-- | arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index 622cc7cc1471..a060718758b6 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -96,10 +96,14 @@ rxd1-skew-ps = <0>; rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; txen-skew-ps = <0>; - txc-skew-ps = <2600>; + txc-skew-ps = <1860>; rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; + rxc-skew-ps = <1860>; }; }; }; |