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| author | Matt Roper <matthew.d.roper@intel.com> | 2023-04-18 15:04:44 -0700 |
|---|---|---|
| committer | Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2023-04-19 15:14:20 -0700 |
| commit | 0c8d9870177a2d7c9e88a2e79dc20950ec84328f (patch) | |
| tree | a3c23f4149865d27aa3139e41f727dfd1cea6d51 /drivers/gpu/drm/i915/display/intel_load_detect.c | |
| parent | 88c487938414c519fdb1c7e55211d8778d3367d0 (diff) | |
drm/i915/mtl: Re-use ADL-P's "DC off" power well
As with ADL-P, MTL's "DC off" power well should be a dependency of the
PGC and PGD power wells, not the entire PG2 well. In fact, the DC5/DC6
requirements between the two platforms are the same, so the Xe_LPD "DC
off" well definition can just be re-used for Xe_LPD+.
Bspec: 49193
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230418220446.2205509-3-radhakrishna.sripada@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_load_detect.c')
0 files changed, 0 insertions, 0 deletions