diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2023-04-18 15:04:43 -0700 |
|---|---|---|
| committer | Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2023-04-19 15:13:58 -0700 |
| commit | 88c487938414c519fdb1c7e55211d8778d3367d0 (patch) | |
| tree | d46a4c2f89ff7214253d5b6a9a69d9fbc3e5c875 /drivers/gpu/drm/i915/display/intel_load_detect.c | |
| parent | 476f62b8a597202a7c97bf50a7f6ece0925ce6f0 (diff) | |
drm/i915: Use separate "DC off" power well for ADL-P and DG2
Although ADL-P and DG2 both use the same general power well setup, the
DC5/DC6 requirements are slightly different which means each platform
should have its own "DC off" power well.
DG2 (i.e., Xe_HPD IP) requires that DC5 be disabled whenever PG2 is
active. However ADL-P (i.e., Xe_LPD IP) only requires DC5/DC6 to be
disabled when the PGC or PGD subwells are active; we should be able to
remain in these DC states when PGB and general PG2 functionality is in
use.
v2: Use dc_of as power well name.
Move xehpd power domain definitions near power well definition.(Imre)
Bspec: 49193
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230418220446.2205509-2-radhakrishna.sripada@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_load_detect.c')
0 files changed, 0 insertions, 0 deletions