diff options
| author | Dave Jiang <[email protected]> | 2022-11-29 10:48:53 -0700 |
|---|---|---|
| committer | Dan Williams <[email protected]> | 2022-12-03 13:40:17 -0800 |
| commit | 2f6e9c305127f8dea4e2d697b4bdd33e126ccbf7 (patch) | |
| tree | 24064175b3c656d412c810d1f376bc75ccf568e1 /drivers/fpga/fpga-mgr.c | |
| parent | bd09626b39dff97779e1543e25e60ab2876e7e88 (diff) | |
cxl/pci: add tracepoint events for CXL RAS
Add tracepoint events for recording the CXL uncorrectable and correctable
errors. For uncorrectable errors, there is additional data of 512B from
the header log register (CXL spec rev3 8.2.4.16.7). The trace event will
intake a dynamic array that will dump the entire Header Log data. If
multiple errors are set in the status register, then the
'first error' field (CXL spec rev3 v8.2.4.16.6) is read from the Error
Capabilities and Control Register in order to determine the error.
This implementation does not include CXL IDE Error details.
Cc: Steven Rostedt <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Dave Jiang <[email protected]>
Reviewed-by: Steven Rostedt (Google) <[email protected]>
Link: https://lore.kernel.org/r/166974413388.1608150.5875712482260436188.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Dan Williams <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-mgr.c')
0 files changed, 0 insertions, 0 deletions