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authorDan Williams <[email protected]>2022-11-29 10:48:48 -0700
committerDan Williams <[email protected]>2022-12-03 13:40:17 -0800
commitbd09626b39dff97779e1543e25e60ab2876e7e88 (patch)
tree42ddd99d1cf5e1a99be5eff8186f746a54d5032e /drivers/fpga/fpga-mgr.c
parenta1554e9cac5ea04aaf2fb2de0df9936a94cb96fc (diff)
cxl/pci: Find and map the RAS Capability Structure
The RAS Capability Structure has some ancillary information that may be relevant with respect to AER events, link and protcol error status registers. Map the RAS Capability Registers in support of defining a 'struct pci_error_handlers' instance for the cxl_pci driver. Reviewed-by: Jonathan Cameron <[email protected]> Signed-off-by: Dave Jiang <[email protected]> Link: https://lore.kernel.org/r/166974412803.1608150.7096566580400947001.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Dan Williams <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-mgr.c')
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