diff options
| author | Geert Uytterhoeven <[email protected]> | 2021-08-10 13:35:03 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2021-08-10 13:35:03 +0200 |
| commit | fb210df33dd969a5cc16aeba809c5e89430f7c4e (patch) | |
| tree | 130591815d485dd6f1d4398e5cdc56f4070f42e5 | |
| parent | b3f894354aa08eb853044a7f5029dbdfc7f3b792 (diff) | |
| parent | 0b256c403d4082bafc681143913442288010277c (diff) | |
Merge tag 'renesas-r9a07g044-dt-binding-defs-tag2' into HEAD
Renesas RZ/G2L DT Binding Definitions Update
Missing definition for the P0_DIV2 core clock on the Renesas RZ/G2L
(R9A07G044) SoC, shared by driver and DT source files.
| -rw-r--r-- | include/dt-bindings/clock/r9a07g044-cpg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h index 0728ad07ff7a..0bb17ff1a01a 100644 --- a/include/dt-bindings/clock/r9a07g044-cpg.h +++ b/include/dt-bindings/clock/r9a07g044-cpg.h @@ -30,6 +30,7 @@ #define R9A07G044_CLK_P2 19 #define R9A07G044_CLK_AT 20 #define R9A07G044_OSCCLK 21 +#define R9A07G044_CLK_P0_DIV2 22 /* R9A07G044 Module Clocks */ #define R9A07G044_CA55_SCLK 0 |