diff options
| author | TungYu Lu <[email protected]> | 2024-06-12 22:34:33 +0800 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2024-06-27 17:10:37 -0400 |
| commit | f86b47bee6343c9f74630d7fc2fb8f5e41db0440 (patch) | |
| tree | 7def90f5f34a9379cc6576ef0087c3ffc958c94b | |
| parent | a4758aa3d1d9ff1c7a05da58387d217c2cd0c38b (diff) | |
drm/amd/display: resync OTG after DIO FIFO resync
[WHY]
Tiled displays showed not aligned on 8K60hz when system resumed
from S3/S4.
[HOW]
Do dc_trigger_sync to re-sync pipes to ensure OTG become synced.
Reviewed-by: Alvin Lee <[email protected]>
Cc: Mario Limonciello <[email protected]>
Cc: Alex Deucher <[email protected]>
Cc: [email protected]
Signed-off-by: Alex Hung <[email protected]>
Signed-off-by: TungYu Lu <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index bdbb4a71651f..fe62478fbcde 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -1254,6 +1254,8 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_ pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); } } + + dc_trigger_sync(dc, dc->current_state); } void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, |