diff options
| author | Leo (Hanghong) Ma <[email protected]> | 2024-06-11 14:12:43 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2024-06-27 17:10:37 -0400 |
| commit | a4758aa3d1d9ff1c7a05da58387d217c2cd0c38b (patch) | |
| tree | d0c7bf9951a39c4e14c0d3db587abc47e13105a8 | |
| parent | 2ffa97c50a8b0598975e47c890032e71958425a0 (diff) | |
drm/amd/display: Always enable HPO for DCN4 dGPU
[WHY && HOW]
Some DP EDID CTS tests fail due to HPO disable, and we should keep it
enable on DCN4 dGPU.
Reviewed-by: Wenjing Liu <[email protected]>
Cc: Mario Limonciello <[email protected]>
Cc: Alex Deucher <[email protected]>
Cc: [email protected]
Signed-off-by: Alex Hung <[email protected]>
Signed-off-by: Leo (Hanghong) Ma <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 42753f56d31d..79a911e1a09a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -408,6 +408,8 @@ void dcn401_init_hw(struct dc *dc) REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } + dcn401_setup_hpo_hw_control(hws, true); + if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index 1cf0608e1980..8159fd838dc3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -137,7 +137,6 @@ static const struct hwseq_private_funcs dcn401_private_funcs = { .program_mall_pipe_config = dcn32_program_mall_pipe_config, .update_force_pstate = dcn32_update_force_pstate, .update_mall_sel = dcn32_update_mall_sel, - .setup_hpo_hw_control = dcn401_setup_hpo_hw_control, .calculate_dccg_k1_k2_values = NULL, .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw, .reset_back_end_for_pipe = dcn20_reset_back_end_for_pipe, |