diff options
| author | Mark Brown <[email protected]> | 2024-05-29 11:24:37 +0100 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2024-05-29 11:24:37 +0100 |
| commit | 4ccaf60062c3682cf4f1438b143c29648edadfda (patch) | |
| tree | 7e8a3e3f46cc02de85fd3e7c48ac9c091e48b58d | |
| parent | d879675bc09a18e2f32c1261cb9e1a15662bc08d (diff) | |
| parent | 9c84429324ea2b5bc537ef8ec7d3727579d37116 (diff) | |
Add support for GPIO based CS
Merge series from Prajna Rajendra Kumar <[email protected]>:
The Microchip PolarFire SoC SPI "hard" controller supports eight
chip selects. However, only one chip select is physically wired.
Therefore, use GPIO descriptors to configure additional chip select
lines.
| -rw-r--r-- | Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml | 29 | ||||
| -rw-r--r-- | drivers/spi/spi-microchip-core.c | 6 |
2 files changed, 31 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml index 74a817cc7d94..ffa8d1b48f8b 100644 --- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml @@ -13,9 +13,6 @@ description: maintainers: - Conor Dooley <[email protected]> -allOf: - - $ref: spi-controller.yaml# - properties: compatible: oneOf: @@ -43,6 +40,32 @@ required: - interrupts - clocks +allOf: + - $ref: spi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: microchip,mpfs-spi + then: + properties: + num-cs: + default: 1 + + - if: + properties: + compatible: + contains: + const: microchip,mpfs-spi + not: + required: + - cs-gpios + then: + properties: + num-cs: + maximum: 1 + unevaluatedProperties: false examples: diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c index 634364c7cfe6..6246254e1dff 100644 --- a/drivers/spi/spi-microchip-core.c +++ b/drivers/spi/spi-microchip-core.c @@ -21,7 +21,7 @@ #include <linux/spi/spi.h> #define MAX_LEN (0xffff) -#define MAX_CS (8) +#define MAX_CS (1) #define DEFAULT_FRAMESIZE (8) #define FIFO_DEPTH (32) #define CLK_GEN_MODE1_MAX (255) @@ -258,6 +258,9 @@ static int mchp_corespi_setup(struct spi_device *spi) struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller); u32 reg; + if (spi_is_csgpiod(spi)) + return 0; + /* * Active high targets need to be specifically set to their inactive * states during probe by adding them to the "control group" & thus @@ -516,6 +519,7 @@ static int mchp_corespi_probe(struct platform_device *pdev) host->num_chipselect = num_cs; host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + host->use_gpio_descriptors = true; host->setup = mchp_corespi_setup; host->bits_per_word_mask = SPI_BPW_MASK(8); host->transfer_one = mchp_corespi_transfer_one; |