diff options
| author | Prajna Rajendra Kumar <[email protected]> | 2024-05-14 11:45:08 +0100 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2024-05-27 01:33:16 +0100 |
| commit | 9c84429324ea2b5bc537ef8ec7d3727579d37116 (patch) | |
| tree | f96d1bd888246c12beba0a01e3606620c418b215 | |
| parent | a7ed3a11202d90939a3d00ffcc8cf50703cb7b35 (diff) | |
spi: spi-microchip-core: Add support for GPIO based CS
The SPI "hard" controller within the PolarFire SoC is capable of
handling eight CS lines, but only one CS line is wired. Therefore, use
GPIO descriptors to configure additional CS lines.
Signed-off-by: Prajna Rajendra Kumar <[email protected]>
Link: https://msgid.link/r/[email protected]
Acked-by: Conor Dooley <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
| -rw-r--r-- | drivers/spi/spi-microchip-core.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c index c10de45aa472..6246254e1dff 100644 --- a/drivers/spi/spi-microchip-core.c +++ b/drivers/spi/spi-microchip-core.c @@ -258,6 +258,9 @@ static int mchp_corespi_setup(struct spi_device *spi) struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller); u32 reg; + if (spi_is_csgpiod(spi)) + return 0; + /* * Active high targets need to be specifically set to their inactive * states during probe by adding them to the "control group" & thus @@ -516,6 +519,7 @@ static int mchp_corespi_probe(struct platform_device *pdev) host->num_chipselect = num_cs; host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + host->use_gpio_descriptors = true; host->setup = mchp_corespi_setup; host->bits_per_word_mask = SPI_BPW_MASK(8); host->transfer_one = mchp_corespi_transfer_one; |