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authorSinthu Raja <[email protected]>2023-09-21 15:30:39 +0530
committerVignesh Raghavendra <[email protected]>2023-10-05 20:44:41 +0530
commit067878e6cd25e071106eb7998165dd3cb46ff2ce (patch)
treeb6797d3ebe33cf617804097f1d699b6b06f90a65
parent73e8ec1b2d101fb030f6906c9d2799bea80e3804 (diff)
arm64: dts: ti: k3-am68-sk: Add DT node for USB
AM68 Starter kit has a USB3 hub that connects to the SerDes0 Lane 2. Update the SerDes configuration to support USB3. Signed-off-by: Sinthu Raja <[email protected]> Signed-off-by: Ravi Gunasekaran <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vignesh Raghavendra <[email protected]>
-rw-r--r--arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts27
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
index 81c2307c77f9..1e1a82f9d2b8 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
@@ -573,6 +573,15 @@
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
};
+
+ serdes0_usb_link: phy@2 {
+ status = "okay";
+ reg = <2>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 3>;
+ };
};
&pcie1_rc {
@@ -582,3 +591,21 @@
phy-names = "pcie-phy";
num-lanes = <2>;
};
+
+&usb_serdes_mux {
+ idle-states = <0>; /* USB0 to SERDES lane 2 */
+};
+
+&usbss0 {
+ status = "okay";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};