1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Rockchip Generic Register Files setup
*
* Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
*/
#include <linux/err.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#define HIWORD_UPDATE(val, mask, shift) \
((val) << (shift) | (mask) << ((shift) + 16))
struct rockchip_grf_value {
const char *desc;
u32 reg;
u32 val;
};
struct rockchip_grf_info {
const struct rockchip_grf_value *values;
int num_values;
};
#define RK3036_GRF_SOC_CON0 0x140
static const struct rockchip_grf_value rk3036_defaults[] __initconst = {
/*
* Disable auto jtag/sdmmc switching that causes issues with the
* clock-framework and the mmc controllers making them unreliable.
*/
{ "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
};
static const struct rockchip_grf_info rk3036_grf __initconst = {
.values = rk3036_defaults,
.num_values = ARRAY_SIZE(rk3036_defaults),
};
#define RK3128_GRF_SOC_CON0 0x140
#define RK3128_GRF_SOC_CON1 0x144
static const struct rockchip_grf_value rk3128_defaults[] __initconst = {
{ "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
{ "vpu main clock", RK3128_GRF_SOC_CON1, HIWORD_UPDATE(0, 1, 10) },
};
static const struct rockchip_grf_info rk3128_grf __initconst = {
.values = rk3128_defaults,
.num_values = ARRAY_SIZE(rk3128_defaults),
};
#define RK3228_GRF_SOC_CON6 0x418
static const struct rockchip_grf_value rk3228_defaults[] __initconst = {
{ "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
};
static const struct rockchip_grf_info rk3228_grf __initconst = {
.values = rk3228_defaults,
.num_values = ARRAY_SIZE(rk3228_defaults),
};
#define RK3288_GRF_SOC_CON0 0x244
#define RK3288_GRF_SOC_CON2 0x24c
static const struct rockchip_grf_value rk3288_defaults[] __initconst = {
{ "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
{ "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
};
static const struct rockchip_grf_info rk3288_grf __initconst = {
.values = rk3288_defaults,
.num_values = ARRAY_SIZE(rk3288_defaults),
};
#define RK3328_GRF_SOC_CON4 0x410
static const struct rockchip_grf_value rk3328_defaults[] __initconst = {
{ "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
};
static const struct rockchip_grf_info rk3328_grf __initconst = {
.values = rk3328_defaults,
.num_values = ARRAY_SIZE(rk3328_defaults),
};
#define RK3368_GRF_SOC_CON15 0x43c
static const struct rockchip_grf_value rk3368_defaults[] __initconst = {
{ "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
};
static const struct rockchip_grf_info rk3368_grf __initconst = {
.values = rk3368_defaults,
.num_values = ARRAY_SIZE(rk3368_defaults),
};
#define RK3399_GRF_SOC_CON7 0xe21c
static const struct rockchip_grf_value rk3399_defaults[] __initconst = {
{ "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },
};
static const struct rockchip_grf_info rk3399_grf __initconst = {
.values = rk3399_defaults,
.num_values = ARRAY_SIZE(rk3399_defaults),
};
#define RK3566_GRF_USB3OTG0_CON1 0x0104
static const struct rockchip_grf_value rk3566_defaults[] __initconst = {
{ "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) },
{ "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) },
{ "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) },
};
static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
.values = rk3566_defaults,
.num_values = ARRAY_SIZE(rk3566_defaults),
};
#define RK3576_SYSGRF_SOC_CON1 0x0004
static const struct rockchip_grf_value rk3576_defaults_sys_grf[] __initconst = {
{ "i3c0 weakpull", RK3576_SYSGRF_SOC_CON1, HIWORD_UPDATE(3, 3, 6) },
{ "i3c1 weakpull", RK3576_SYSGRF_SOC_CON1, HIWORD_UPDATE(3, 3, 8) },
};
static const struct rockchip_grf_info rk3576_sysgrf __initconst = {
.values = rk3576_defaults_sys_grf,
.num_values = ARRAY_SIZE(rk3576_defaults_sys_grf),
};
#define RK3576_IOCGRF_MISC_CON 0x04F0
static const struct rockchip_grf_value rk3576_defaults_ioc_grf[] __initconst = {
{ "jtag switching", RK3576_IOCGRF_MISC_CON, HIWORD_UPDATE(0, 1, 1) },
};
static const struct rockchip_grf_info rk3576_iocgrf __initconst = {
.values = rk3576_defaults_ioc_grf,
.num_values = ARRAY_SIZE(rk3576_defaults_ioc_grf),
};
#define RK3588_GRF_SOC_CON6 0x0318
static const struct rockchip_grf_value rk3588_defaults[] __initconst = {
{ "jtag switching", RK3588_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 14) },
};
static const struct rockchip_grf_info rk3588_sysgrf __initconst = {
.values = rk3588_defaults,
.num_values = ARRAY_SIZE(rk3588_defaults),
};
static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
{
.compatible = "rockchip,rk3036-grf",
.data = (void *)&rk3036_grf,
}, {
.compatible = "rockchip,rk3128-grf",
.data = (void *)&rk3128_grf,
}, {
.compatible = "rockchip,rk3228-grf",
.data = (void *)&rk3228_grf,
}, {
.compatible = "rockchip,rk3288-grf",
.data = (void *)&rk3288_grf,
}, {
.compatible = "rockchip,rk3328-grf",
.data = (void *)&rk3328_grf,
}, {
.compatible = "rockchip,rk3368-grf",
.data = (void *)&rk3368_grf,
}, {
.compatible = "rockchip,rk3399-grf",
.data = (void *)&rk3399_grf,
}, {
.compatible = "rockchip,rk3566-pipe-grf",
.data = (void *)&rk3566_pipegrf,
}, {
.compatible = "rockchip,rk3576-sys-grf",
.data = (void *)&rk3576_sysgrf,
}, {
.compatible = "rockchip,rk3576-ioc-grf",
.data = (void *)&rk3576_iocgrf,
}, {
.compatible = "rockchip,rk3588-sys-grf",
.data = (void *)&rk3588_sysgrf,
},
{ /* sentinel */ },
};
static int __init rockchip_grf_init(void)
{
const struct rockchip_grf_info *grf_info;
const struct of_device_id *match;
struct device_node *np;
struct regmap *grf;
int ret, i;
np = of_find_matching_node_and_match(NULL, rockchip_grf_dt_match,
&match);
if (!np)
return -ENODEV;
if (!match || !match->data) {
pr_err("%s: missing grf data\n", __func__);
of_node_put(np);
return -EINVAL;
}
grf_info = match->data;
grf = syscon_node_to_regmap(np);
of_node_put(np);
if (IS_ERR(grf)) {
pr_err("%s: could not get grf syscon\n", __func__);
return PTR_ERR(grf);
}
for (i = 0; i < grf_info->num_values; i++) {
const struct rockchip_grf_value *val = &grf_info->values[i];
pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__,
val->desc, val->reg, val->val);
ret = regmap_write(grf, val->reg, val->val);
if (ret < 0)
pr_err("%s: write to %#6x failed with %d\n",
__func__, val->reg, ret);
}
return 0;
}
postcore_initcall(rockchip_grf_init);
|