Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sophgo SG2042 PLL Clock Generator

maintainers:
  - Chen Wang <unicorn_wang@outlook.com>

properties:
  compatible:
    const: sophgo,sg2042-pll

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
      - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
      - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)

  clock-names:
    items:
      - const: cgi_main
      - const: cgi_dpll0
      - const: cgi_dpll1

  '#clock-cells':
    const: 1
    description:
      See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller@10000000 {
      compatible = "sophgo,sg2042-pll";
      reg = <0x10000000 0x10000>;
      clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
      clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
      #clock-cells = <1>;
    };