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2023-04-26Merge tag 'kvm-x86-selftests-6.4' of https://github.com/kvm-x86/linux into HEADPaolo Bonzini11-93/+295
KVM selftests, and an AMX/XCR0 bugfix, for 6.4: - Don't advertise XTILE_CFG in KVM_GET_SUPPORTED_CPUID if XTILE_DATA is not being reported due to userspace not opting in via prctl() - Overhaul the AMX selftests to improve coverage and cleanup the test - Misc cleanups
2023-04-26Merge tag 'kvm-x86-pmu-6.4' of https://github.com/kvm-x86/linux into HEADPaolo Bonzini3-154/+373
KVM x86 PMU changes for 6.4: - Disallow virtualizing legacy LBRs if architectural LBRs are available, the two are mutually exclusive in hardware - Disallow writes to immutable feature MSRs (notably PERF_CAPABILITIES) after KVM_RUN, and overhaul the vmx_pmu_caps selftest to better validate PERF_CAPABILITIES - Apply PMU filters to emulated events and add test coverage to the pmu_event_filter selftest - Misc cleanups and fixes
2023-04-21Merge branch kvm-arm64/smccc-filtering into kvmarm-master/nextMarc Zyngier4-19/+315
* kvm-arm64/smccc-filtering: : . : SMCCC call filtering and forwarding to userspace, courtesy of : Oliver Upton. From the cover letter: : : "The Arm SMCCC is rather prescriptive in regards to the allocation of : SMCCC function ID ranges. Many of the hypercall ranges have an : associated specification from Arm (FF-A, PSCI, SDEI, etc.) with some : room for vendor-specific implementations. : : The ever-expanding SMCCC surface leaves a lot of work within KVM for : providing new features. Furthermore, KVM implements its own : vendor-specific ABI, with little room for other implementations (like : Hyper-V, for example). Rather than cramming it all into the kernel we : should provide a way for userspace to handle hypercalls." : . KVM: selftests: Fix spelling mistake "KVM_HYPERCAL_EXIT_SMC" -> "KVM_HYPERCALL_EXIT_SMC" KVM: arm64: Test that SMC64 arch calls are reserved KVM: arm64: Prevent userspace from handling SMC64 arch range KVM: arm64: Expose SMC/HVC width to userspace KVM: selftests: Add test for SMCCC filter KVM: selftests: Add a helper for SMCCC calls with SMC instruction KVM: arm64: Let errors from SMCCC emulation to reach userspace KVM: arm64: Return NOT_SUPPORTED to guest for unknown PSCI version KVM: arm64: Introduce support for userspace SMCCC filtering KVM: arm64: Add support for KVM_EXIT_HYPERCALL KVM: arm64: Use a maple tree to represent the SMCCC filter KVM: arm64: Refactor hvc filtering to support different actions KVM: arm64: Start handling SMCs from EL1 KVM: arm64: Rename SMC/HVC call handler to reflect reality KVM: arm64: Add vm fd device attribute accessors KVM: arm64: Add a helper to check if a VM has ran once KVM: x86: Redefine 'longmode' as a flag for KVM_EXIT_HYPERCALL Signed-off-by: Marc Zyngier <[email protected]>
2023-04-21Merge branch kvm-arm64/selftest/misc-6.4 into kvmarm-master/nextMarc Zyngier1-5/+5
* kvm-arm64/selftest/misc-6.4: : . : Misc selftest updates for 6.4 : : - Add comments for recently added ID registers : . KVM: selftests: Comment newly defined aarch64 ID registers Signed-off-by: Marc Zyngier <[email protected]>
2023-04-21Merge branch kvm-arm64/selftest/lpa into kvmarm-master/nextMarc Zyngier2-10/+30
* kvm-arm64/selftest/lpa: : . : Selftest fixes addressing PTE and TTBR0_EL1 encodings for : 52bit PAs : . KVM: selftests: arm64: Fix ttbr0_el1 encoding for PA bits > 48 KVM: selftests: arm64: Fix pte encode/decode for PA bits > 48 KVM: selftests: Fixup config fragment for access_tracking_perf_test Signed-off-by: Marc Zyngier <[email protected]>
2023-04-14KVM: selftests: Test the PMU event "Instructions retired"Aaron Lewis1-2/+32
Add testing for the event "Instructions retired" (0xc0) in the PMU event filter on both Intel and AMD to ensure that the event doesn't count when it is disallowed. Unlike most of the other events, the event "Instructions retired" will be incremented by KVM when an instruction is emulated. Test that this case is being properly handled and that KVM doesn't increment the counter when that event is disallowed. Signed-off-by: Aaron Lewis <[email protected]> Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-14KVM: selftests: Copy full counter values from guest in PMU event filter testSean Christopherson1-90/+80
Use a single struct to track all PMC event counts in the PMU filter test, and copy the full struct to/from the guest when running and measuring each guest workload. Using a common struct avoids naming conflicts, e.g. the loads/stores testcase has claimed "perf_counter", and eliminates the unnecessary truncation of the counter values when they are propagated from the guest MSRs to the host structs. Zero the struct before running the guest workload to ensure that the test doesn't get a false pass due to consuming data from a previous run. Link: https://lore.kernel.org/r/[email protected] Reviewed by: Aaron Lewis <[email protected]> Signed-off-by: Sean Christopherson <[email protected]>
2023-04-14KVM: selftests: Use error codes to signal errors in PMU event filter testSean Christopherson1-8/+8
Use '0' to signal success and '-errno' to signal failure in the PMU event filter test so that the values are slightly less magical/arbitrary. Using '0' in the error paths is especially confusing as understanding it's an error value requires following the breadcrumbs to the host code that ultimately consumes the value. Arguably there should also be a #define for "success", but 0/-errno is a common enough pattern that defining another macro on top would likely do more harm than good. Link: https://lore.kernel.org/r/[email protected] Reviewed by: Aaron Lewis <[email protected]> Signed-off-by: Sean Christopherson <[email protected]>
2023-04-14KVM: selftests: Print detailed info in PMU event filter assertsAaron Lewis1-6/+5
Provide the actual vs. expected count in the PMU event filter test's asserts instead of relying on pr_info() to provide the context, e.g. so that all information needed to triage a failure is readily available even if the environment in which the test is run captures only the assert itself. Signed-off-by: Aaron Lewis <[email protected]> [sean: rewrite changelog] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-14KVM: selftests: Add helpers for PMC asserts in PMU event filter testAaron Lewis1-25/+27
Add helper macros to consolidate the asserts that a PMC is/isn't counting (branch) instructions retired. This will make it easier to add additional asserts related to counting instructions later on. No functional changes intended. Signed-off-by: Aaron Lewis <[email protected]> [sean: add "INSTRUCTIONS", massage changelog] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-14KVM: selftests: Add a common helper for the PMU event filter guest codeAaron Lewis1-11/+18
Split out the common parts of the Intel and AMD guest code in the PMU event filter test into a helper function. This is in preparation for adding additional counters to the test. No functional changes intended. Signed-off-by: Aaron Lewis <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-14KVM: selftests: Fix spelling mistake "perrmited" -> "permitted"Colin Ian King1-1/+1
There is a spelling mistake in a test report message. Fix it. Signed-off-by: Colin Ian King <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-11KVM: selftests: Add test to verify KVM's supported XCR0Aaron Lewis3-0/+153
Check both architectural rules and KVM's ABI for KVM_GET_SUPPORTED_CPUID to ensure the supported xfeatures[1] don't violate any of them. The architectural rules[2] and KVM's contract with userspace ensure for a given feature, e.g. sse, avx, amx, etc... their associated xfeatures are either all sets or none of them are set, and any dependencies are enabled if needed. [1] EDX:EAX of CPUID.(EAX=0DH,ECX=0) [2] SDM vol 1, 13.3 ENABLING THE XSAVE FEATURE SET AND XSAVE-ENABLED FEATURES Cc: Mingwei Zhang <[email protected]> Signed-off-by: Aaron Lewis <[email protected]> [sean: expand comments, use a fancy X86_PROPERTY] Reviewed-by: Aaron Lewis <[email protected]> Tested-by: Aaron Lewis <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-11KVM: selftests: Add all known XFEATURE masks to common codeAaron Lewis2-30/+33
Add all known XFEATURE masks to processor.h to make them more broadly available in KVM selftests. Relocate and clean up the exiting AMX (XTILE) defines in processor.h, e.g. drop the intermediate define and use BIT_ULL. Signed-off-by: Aaron Lewis <[email protected]> Reviewed-by: Aaron Lewis <[email protected]> Tested-by: Aaron Lewis <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-11KVM: selftests: Rework dynamic XFeature helper to take mask, not bitSean Christopherson3-11/+14
Take the XFeature mask in __vm_xsave_require_permission() instead of the bit so that there's no need to define macros for both the bit and the mask. Asserting that only a single bit is set and retrieving said bit is easy enough via log2 helpers. Opportunistically clean up the error message for the ARCH_REQ_XCOMP_GUEST_PERM sanity check. Reviewed-by: Aaron Lewis <[email protected]> Tested-by: Aaron Lewis <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-11KVM: selftests: Move XGETBV and XSETBV helpers to common codeAaron Lewis2-21/+21
The instructions XGETBV and XSETBV are useful to other tests. Move them to processor.h to make them more broadly available. No functional change intended. Reviewed-by: Jim Mattson <[email protected]> Signed-off-by: Aaron Lewis <[email protected]> Reviewed-by: Mingwei Zhang <[email protected]> [sean: reword shortlog] Reviewed-by: Aaron Lewis <[email protected]> Tested-by: Aaron Lewis <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-08KVM: selftests: Fix spelling mistake "KVM_HYPERCAL_EXIT_SMC" -> ↵Colin Ian King1-1/+1
"KVM_HYPERCALL_EXIT_SMC" There is a spelling mistake in a test assert message. Fix it. Signed-off-by: Colin Ian King <[email protected]> Reviewed-by: Oliver Upton <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-04-08KVM: arm64: Test that SMC64 arch calls are reservedOliver Upton1-0/+8
Assert that the SMC64 view of the Arm architecture range is reserved by KVM and cannot be filtered by userspace. Signed-off-by: Oliver Upton <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-04-06KVM: selftests: Verify LBRs are disabled if vPMU is disabledSean Christopherson1-0/+29
Verify that disabling the guest's vPMU via CPUID also disables LBRs. KVM has had at least one bug where LBRs would remain enabled even though the intent was to disable everything PMU related. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Add negative testcase for PEBS format in PERF_CAPABILITIESSean Christopherson1-0/+10
Expand the immutable features sub-test for PERF_CAPABILITIES to verify KVM rejects any attempt to use a PEBS format other than the host's. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Refactor LBR_FMT test to avoid use of separate macroSean Christopherson1-7/+6
Rework the LBR format test to use the bitfield instead of a separate mask macro, mainly so that adding a nearly-identical PEBS format test doesn't have to copy-paste-tweak the macro too. No functional change intended. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Drop "all done!" printf() from PERF_CAPABILITIES testSean Christopherson1-2/+0
Drop the arbitrary "done" message from the VMX PMU caps test, it's pretty obvious the test is done when the process exits. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Test post-KVM_RUN writes to PERF_CAPABILITIESSean Christopherson1-0/+13
Now that KVM disallows changing PERF_CAPABILITIES after KVM_RUN, expand the host side checks to verify KVM rejects any attempts to change bits from userspace. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Expand negative testing of guest writes to PERF_CAPABILITIESSean Christopherson1-7/+54
Test that the guest can't write 0 to PERF_CAPABILITIES, can't write the current value, and can't toggle _any_ bits. There is no reason to special case the LBR format. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Test all immutable non-format bits in PERF_CAPABILITIESSean Christopherson1-3/+27
Add negative testing of all immutable bits in PERF_CAPABILITIES, i.e. single bits that are reserved-0 or are effectively reserved-1 by KVM. Omit LBR and PEBS format bits from the test as it's easier to test them manually than it is to add safeguards to the comment path, e.g. toggling a single bit can yield a format of '0', which is legal as a "disable" value. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Test all fungible features in PERF_CAPABILITIESSean Christopherson1-5/+24
Verify that userspace can set all fungible features in PERF_CAPABILITIES. Drop the now unused #define of the "full-width writes" flag. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Drop now-redundant checks on PERF_CAPABILITIES writesSean Christopherson1-6/+0
Now that vcpu_set_msr() verifies the expected "read what was wrote" semantics of all durable MSRs, including PERF_CAPABILITIES, drop the now-redundant manual checks in the VMX PMU caps test. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Verify KVM preserves userspace writes to "durable" MSRsSean Christopherson1-1/+16
Assert that KVM provides "read what you wrote" semantics for all "durable" MSRs (for lack of a better name). The extra coverage is cheap from a runtime performance perspective, and verifying the behavior in the common helper avoids gratuitous copy+paste in individual tests. Note, this affects all tests that set MSRs from userspace! Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Print out failing MSR and value in vcpu_set_msr()Sean Christopherson1-8/+24
Reimplement vcpu_set_msr() as a macro and pretty print the failing MSR (when possible) and the value if KVM_SET_MSRS fails instead of using the using the standard KVM_IOCTL_ERROR(). KVM_SET_MSRS is somewhat odd in that it returns the index of the last successful write, i.e. will be '0' on failure barring an entirely different KVM bug. And for writing MSRs, the MSR being written and the value being written are almost always relevant to the failure, i.e. just saying "failed!" doesn't help debug. Place the string goo in a separate macro in anticipation of using it to further expand MSR testing. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Assert that full-width PMC writes are supported if PDCM=1Sean Christopherson1-0/+3
KVM emulates full-width PMC writes in software, assert that KVM reports full-width writes as supported if PERF_CAPABILITIES is supported. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Move 0/initial value PERF_CAPS checks to dedicated sub-testSean Christopherson1-6/+19
Use a separate sub-test to verify userspace can clear PERF_CAPABILITIES and restore it to the KVM-supported value, as the testcase isn't unique to the LBR format. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-06KVM: selftests: Split PMU caps sub-tests to avoid writing MSR after KVM_RUNSean Christopherson1-20/+31
Split the PERF_CAPABILITIES subtests into two parts so that the LBR format testcases don't execute after KVM_RUN. Similar to the guest CPUID model, KVM will soon disallow changing PERF_CAPABILITIES after KVM_RUN, at which point attempting to set the MSR after KVM_RUN will yield false positives and/or false negatives depending on what the test is trying to do. Land the LBR format test in a more generic "immutable features" test in anticipation of expanding its scope to other immutable features. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-05KVM: selftests: Close opened file descriptor in stable_tsc_check_supported()Hao Ge1-2/+6
Close the "current_clocksource" file descriptor before returning or exiting from stable_tsc_check_supported() in vmx_nested_tsc_scaling_test. Signed-off-by: Hao Ge <[email protected]> Reviewed-by: Vipin Sharma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-04-05KVM: selftests: Add test for SMCCC filterOliver Upton2-0/+261
Add a selftest for the SMCCC filter, ensuring basic UAPI constraints (e.g. reserved ranges, non-overlapping ranges) are upheld. Additionally, test that the DENIED and FWD_TO_USER work as intended. Signed-off-by: Oliver Upton <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-04-05KVM: selftests: Add a helper for SMCCC calls with SMC instructionOliver Upton2-19/+46
Build a helper for doing SMCs in selftests by macro-izing the current HVC implementation and taking the conduit instruction as an argument. Signed-off-by: Oliver Upton <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-30KVM: selftests: Comment newly defined aarch64 ID registersMark Brown1-5/+5
All otherwise unspecified aarch64 ID registers should be read as zero so we cover the whole ID register space in the get-reg-list test but we've added comments for those that have been named. Add comments for ID_AA64PFR2_EL1, ID_AA64SMFR0_EL1, ID_AA64ISAR2_EL1, ID_AA64MMFR3_EL1 and ID_AA64MMFR4_EL1 which have been defined since the comments were added so someone looking for them will see that they are covered. Signed-off-by: Mark Brown <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-30KVM: selftests: arm64: Fix ttbr0_el1 encoding for PA bits > 48Ryan Roberts1-2/+5
Bits [51:48] of the pgd address are stored at bits [5:2] of ttbr0_el1. page_table_test stores its page tables at the far end of IPA space so was tripping over this when run on a system that supports FEAT_LPA (or FEAT_LPA2). Signed-off-by: Ryan Roberts <[email protected]> Reviewed-by: Oliver Upton <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-30KVM: selftests: arm64: Fix pte encode/decode for PA bits > 48Ryan Roberts1-8/+24
The high bits [51:48] of a physical address should appear at [15:12] in a 64K pte, not at [51:48] as was previously being programmed. Fix this with new helper functions that do the conversion correctly. This also sets us up nicely for adding LPA2 encodings in future. Fixes: 7a6629ef746d ("kvm: selftests: add virt mem support for aarch64") Signed-off-by: Ryan Roberts <[email protected]> Reviewed-by: Oliver Upton <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-30KVM: selftests: Fixup config fragment for access_tracking_perf_testRyan Roberts1-0/+1
access_tracking_perf_test requires CONFIG_IDLE_PAGE_TRACKING. However this is missing from the config fragment, so add it in so that this test is no longer skipped. Signed-off-by: Ryan Roberts <[email protected]> Reviewed-by: Sean Christopherson <[email protected]> Reviewed-by: Oliver Upton <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-30KVM: arm64: selftests: Augment existing timer test to handle variable offsetMarc Zyngier1-1/+15
Allow a user to specify the global offset on the command-line. Reviewed-by: Colton Lewis <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-30KVM: arm64: selftests: Deal with spurious timer interruptsMarc Zyngier1-15/+25
Make sure the timer test can properly handle a spurious timer interrupt, something that is far from being unlikely. This involves checking for the GIC IAR return value (don't bother handling the interrupt if it was spurious) as well as the timer control register (don't do anything if the interrupt is masked or the timer disabled). Take this opportunity to rewrite the timer handler in a more readable way. This solves a bunch of failures that creep up on systems that are slow to retire the interrupt, something that the GIC architecture makes no guarantee about. Reviewed-by: Colton Lewis <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-30KVM: arm64: selftests: Add physical timer registers to the sysreg listMarc Zyngier1-1/+4
Now that KVM exposes CNTPCT_EL0, CNTP_CTL_EL0 and CNT_CVAL_EL0 to userspace, add them to the get-reg-list selftest. Reviewed-by: Colton Lewis <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-24KVM: selftests: Check that XTILEDATA supports XFDAaron Lewis2-0/+2
Check that XTILEDATA supports XFD. In amx_test, add the requirement that the guest allows the xfeature, XTILEDATA, to be set in XFD. Otherwise, the test may fail. Signed-off-by: Aaron Lewis <[email protected]> Signed-off-by: Mingwei Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-03-24KVM: selftests: Check that the palette table exists before using itAaron Lewis2-0/+6
Check that the palette table exists before using it. The maximum number of AMX palette tables is enumerated by CPUID.1DH:EAX. Assert that the palette used in amx_test, CPUID.1DH.1H, does not exceed that maximum. Signed-off-by: Aaron Lewis <[email protected]> Signed-off-by: Mingwei Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-03-24KVM: selftests: Move XSAVE and OSXSAVE CPUID checks into AMX's init_regs()Aaron Lewis1-7/+3
Move the checks on XSAVE and OSXSAVE into init_regs() so that the XSAVE check is done before setting CR4.OSXSAVE, i.e. before a potential #GP, and so that the OSXSAVE check is performend immediately after enabling XSAVE in CR4. Signed-off-by: Aaron Lewis <[email protected]> Signed-off-by: Mingwei Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] [sean: keep XSAVE check, rewrite changelog accordingly] Signed-off-by: Sean Christopherson <[email protected]>
2023-03-24KVM: selftests: Assert that both XTILE{CFG,DATA} are XSAVE-enabledAaron Lewis1-1/+1
Assert that both XTILE{CFG,DATA} are written and read back via XSETBV and XGETBV respectively. The original check in amx_test only ensures at least one of the XTILE bits are set, XTILECFG or XTILEDATA, when it really should be checking that both are set. Fixes: bf70636d9443 ("selftest: kvm: Add amx selftest") Signed-off-by: Aaron Lewis <[email protected]> Signed-off-by: Mingwei Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] [sean: massage changelog] Signed-off-by: Sean Christopherson <[email protected]>
2023-03-24KVM: selftests: Assert that XTILE is XSAVE-enabledAaron Lewis1-6/+1
Assert that XTILE is XSAVE-enabled. check_xsave_supports_xtile() doesn't actually check anything since its return value is not used. Add the intended assert. Opportunistically, move the assert to a more appropriate location: immediately after XSETBV and remove check_xsave_supports_xtile(). Fixes: 5dc19f1c7dd3 ("KVM: selftests: Convert AMX test to use X86_PROPRETY_XXX") Signed-off-by: Aaron Lewis <[email protected]> Signed-off-by: Mingwei Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Christopherson <[email protected]>
2023-03-24KVM: selftests: Verify XTILE_DATA in XSTATE isn't affected by IA32_XFDMingwei Zhang1-0/+10
Add asserts to verify the XSTATE metadata for XTILE_DATA isn't affected by disabling AMX tile data via IA32_XFD. XFD doesn't intercept XSAVE, it only prevents setting bits in XCR0, i.e. regardless of XFD, AMX state is managed by XSAVE/XRSTOR as long as the corresponding bits are set XCR0. Signed-off-by: Mingwei Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] [sean: massage changelog] Signed-off-by: Sean Christopherson <[email protected]>
2023-03-24KVM: selftests: Assert that XTILE_DATA is set in IA32_XFD on #NMMingwei Zhang1-0/+2
Add an extra check to IA32_XFD to ensure that XTILE_DATA is actually set, i.e. is consistent with the AMX architecture. In addition, repeat the checks after the guest/host world switch to ensure the values of IA32_XFD and IA32_XFD_ERR are well preserved. Signed-off-by: Mingwei Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] [sean: massage changelog] Signed-off-by: Sean Christopherson <[email protected]>
2023-03-24KVM: selftests: Add check of CR0.TS in the #NM handler in amx_testMingwei Zhang1-0/+1
Be extra paranoid and assert that CR0.TS is clear when verifying the #NM in the AMX test is due to the expected XFeature Disable error, i.e. that the #NM isn't due to CR0.TS=1. Signed-off-by: Mingwei Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] [sean: reword changelog to make it clear this is pure paranoia] Signed-off-by: Sean Christopherson <[email protected]>