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2022-09-16crypto: hisilicon/qm - add UACCE_CMD_QM_SET_QP_INFO supportWeili Qian1-1/+16
To be compatible with accelerator devices of different versions, 'UACCE_CMD_QM_SET_QP_INFO' ioctl is added to obtain queue information in userspace, including queue depth and buffer description size. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2021-03-26crypto: hisilicon/qm - add queue isolation support for Kunpeng930Weili Qian1-0/+1
Kunpeng930 supports doorbell isolation to ensure that each queue has an independent doorbell address space. Signed-off-by: Weili Qian <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2020-02-22crypto: hisilicon - register zip engine to uacceZhangfei Gao1-0/+23
Register qm to uacce framework for user crypto driver Reviewed-by: Greg Kroah-Hartman <[email protected]> Reviewed-by: Jonathan Cameron <[email protected]> Signed-off-by: Zhangfei Gao <[email protected]> Signed-off-by: Zhou Wang <[email protected]> Signed-off-by: Herbert Xu <[email protected]>
2020-02-22uacce: add uacce driverKenneth Lee1-0/+38
Uacce (Unified/User-space-access-intended Accelerator Framework) targets to provide Shared Virtual Addressing (SVA) between accelerators and processes. So accelerator can access any data structure of the main cpu. This differs from the data sharing between cpu and io device, which share only data content rather than address. Since unified address, hardware and user space of process can share the same virtual address in the communication. Uacce create a chrdev for every registration, the queue is allocated to the process when the chrdev is opened. Then the process can access the hardware resource by interact with the queue file. By mmap the queue file space to user space, the process can directly put requests to the hardware without syscall to the kernel space. The IOMMU core only tracks mm<->device bonds at the moment, because it only needs to handle IOTLB invalidation and PASID table entries. However uacce needs a finer granularity since multiple queues from the same device can be bound to an mm. When the mm exits, all bound queues must be stopped so that the IOMMU can safely clear the PASID table entry and reallocate the PASID. An intermediate struct uacce_mm links uacce devices and queues. Note that an mm may be bound to multiple devices but an uacce_mm structure only ever belongs to a single device, because we don't need anything more complex (if multiple devices are bound to one mm, then we'll create one uacce_mm for each bond). uacce_device --+-- uacce_mm --+-- uacce_queue | '-- uacce_queue | '-- uacce_mm --+-- uacce_queue +-- uacce_queue '-- uacce_queue Reviewed-by: Greg Kroah-Hartman <[email protected]> Reviewed-by: Jonathan Cameron <[email protected]> Signed-off-by: Kenneth Lee <[email protected]> Signed-off-by: Zaibo Xu <[email protected]> Signed-off-by: Zhou Wang <[email protected]> Signed-off-by: Jean-Philippe Brucker <[email protected]> Signed-off-by: Zhangfei Gao <[email protected]> Signed-off-by: Herbert Xu <[email protected]>