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2021-10-16clocksource/drivers/arc_timer: Eliminate redefined macro errorRandy Dunlap1-2/+2
In drivers/clocksource/, 3 drivers use "TIMER_CTRL_IE" with 3 different values. Two of them (mps2-timer.c and timer-sp804.c/timer-sp.h) are localized and left unmodifed. One of them uses a shared header file (<soc/arc/timers.h>), which is what is causing the "redefined" warnings, so change the macro name in that driver only. Also change the TIMER_CTRL_NH macro name. Both macro names are prefixed with "ARC_" to reduce the likelihood of future name collisions. In file included from ../drivers/clocksource/timer-sp804.c:24: ../drivers/clocksource/timer-sp.h:25: error: "TIMER_CTRL_IE" redefined [-Werror] 25 | #define TIMER_CTRL_IE (1 << 5) /* VR */ ../include/soc/arc/timers.h:20: note: this is the location of the previous definition 20 | #define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ Fixes: b26c2e3823ba ("ARC: breakout timer include code into separate header") Signed-off-by: Randy Dunlap <[email protected]> Cc: Vineet Gupta <[email protected]> Cc: [email protected] Cc: Daniel Lezcano <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Shahab Vahedi <[email protected]> Acked-by: Vineet Gupta <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-08-12include/: replace HTTP links with HTTPS onesAlexander A. Klimov1-1/+1
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Signed-off-by: Alexander A. Klimov <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Reviewed-by: Kees Cook <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Linus Torvalds <[email protected]>
2019-08-26ARCv2: IDU-intc: Add support for edge-triggered interruptsMischa Jonker1-0/+11
This adds support for an optional extra interrupt cell to specify edge vs level triggered. It is backward compatible with dts files with only one cell, and will default to level-triggered in such a case. Note that I had to make a change to idu_irq_set_affinity as well, as this function was setting the interrupt type to "level" unconditionally, since this was the only type supported previously. Signed-off-by: Mischa Jonker <[email protected]> Reviewed-by: Vineet Gupta <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner3-13/+3
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Enrico Weigelt <[email protected]> Reviewed-by: Kate Stewart <[email protected]> Reviewed-by: Allison Randal <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-02-28ARC: mcip: update MCIP debug mask when the new cpu came onlineEugeniy Paltsev1-0/+2
As of today we use hardcoded MCIP debug mask, so if we launch kernel via debugger and kick fever cores than HW has all cpus hang at the momemt of setup MCIP debug mask. So update MCIP debug mask when the new cpu came online, instead of use hardcoded MCIP debug mask. Signed-off-by: Eugeniy Paltsev <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2018-02-28ARC: mcip: halt GFRC counter when ARC cores haltEugeniy Paltsev1-0/+3
In SMP systems, GFRC is used for clocksource. However by default the counter keeps running even when core is halted (say when debugging via a JTAG debugger). This confuses Linux timekeeping and triggers flase RCU stall splat such as below: | [ARCLinux]# while true; do ./shm_open_23-1.run-test ; done | Running with 1000 processes for 1000 objects | hrtimer: interrupt took 485060 ns | | create_cnt: 1000 | Running with 1000 processes for 1000 objects | [ARCLinux]# INFO: rcu_preempt self-detected stall on CPU | 2-...: (1 GPs behind) idle=a01/1/0 softirq=135770/135773 fqs=0 | INFO: rcu_preempt detected stalls on CPUs/tasks: | 0-...: (1 GPs behind) idle=71e/0/0 softirq=135264/135264 fqs=0 | 2-...: (1 GPs behind) idle=a01/1/0 softirq=135770/135773 fqs=0 | 3-...: (1 GPs behind) idle=4e0/0/0 softirq=134304/134304 fqs=0 | (detected by 1, t=13648 jiffies, g=31493, c=31492, q=1) Starting from ARC HS v3.0 it's possible to tie GFRC to state of up-to 4 ARC cores with help of GFRC's CORE register where we set a mask for cores which state we need to rely on. We update cpu mask every time new cpu came online instead of using hardcoded one or using mask generated from "possible_cpus" as we want it set correctly even if we run kernel on HW which has fewer cores than expected (or we launch kernel via debugger and kick fever cores than HW has) Note that GFRC halts when all cores have halted and thus relies on programming of Inter-Core-dEbug register to halt all cores when one halts. Signed-off-by: Alexey Brodkin <[email protected]> Signed-off-by: Eugeniy Paltsev <[email protected]> Signed-off-by: Vineet Gupta <[email protected]> [vgupta: rewrote changelog]
2017-02-06ARCv2: IDU-intc: Use build registers for getting numbers of interruptsYuriy Kolerov1-0/+17
This enhancement is needed to allow masking all available common interrupts in IDU interrupt controller in boot time since the kernel can discover a number of them from the build register. Also now there is no need to specify in device tree a list of used core interrupts by IDU. E.g. before: idu_intc: idu-interrupt-controller { compatible = "snps,archs-idu-intc"; interrupt-controller; interrupt-parent = <&core_intc>; #interrupt-cells = <2>; interrupts = <24 25 26 27 28 29 30 31>; }; and after: idu_intc: idu-interrupt-controller { compatible = "snps,archs-idu-intc"; interrupt-controller; interrupt-parent = <&core_intc>; #interrupt-cells = <2>; }; Signed-off-by: Yuriy Kolerov <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2017-01-24ARCv2: MCIP: update the BCR per current changesVineet Gupta1-8/+8
Signed-off-by: Vineet Gupta <[email protected]>
2016-11-30ARC: breakout timer include code into separate header ...Vineet Gupta1-0/+38
... which allows for use in drivers/clocksource later Signed-off-by: Vineet Gupta <[email protected]>
2016-11-30ARC: move mcip.h into include/soc and adjust the includesVineet Gupta1-0/+103
Also remove the dependency on ARCv2, to increase compile coverage for !ARCV2 builds Acked-by: Daniel Lezcano <[email protected]> Signed-off-by: Vineet Gupta <[email protected]>
2016-11-30ARC: breakout aux handling into a separate headerVineet Gupta1-0/+63
ARC timers use aux registers for programming and this paves way for moving ARC timer drivers into drivers/clocksource Signed-off-by: Vineet Gupta <[email protected]>
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