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2024-04-05dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on ↵Neil Armstrong1-0/+4
SM8[456]50 SoCs The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-1-3ec0a966d52f@linaro.org Signed-off-by: Vinod Koul <[email protected]>
2022-11-24dt-bindings: phy: qcom,qmp-usb3-dp: fix sc8280xp bindingJohan Hovold1-0/+20
The current QMP USB3-DP PHY bindings are based on the original MSM8996 binding which provided multiple PHYs per IP block and these in turn were described by child nodes. The QMP USB3-DP PHY block provides a single multi-protocol PHY and even if some resources are only used by either the USB or DP part of the device there is no real benefit in describing these resources in child nodes. The original MSM8996 binding also ended up describing the individual register blocks as belonging to either the wrapper node or the PHY child nodes. This is an unnecessary level of detail which has lead to problems when later IP blocks using different register layouts have been forced to fit the original mould rather than updating the binding. The bindings are arguable also incomplete as they only the describe register blocks used by the current Linux drivers (e.g. does not include the PCS LANE registers). This is specifically true for later USB4-USB3-DP QMP PHYs where the TX registers are used by both the USB3 and DP parts of the PHY (and where the USB4 part of the PHY was not covered by the binding at all). Notably there are also no DP "RX" (sic) registers as described by the current bindings and the DP "PCS" region is really a set of DP_PHY registers. Add a new binding for the USB4-USB3-DP QMP PHYs found on SC8280XP which further bindings can be based on. Note that the binding uses a PHY index to access either the USB3 or DP part of the PHY and that this can later be used also for the USB4 part if needed. Similarly, the clock inputs and outputs can later be extended to support USB4. Also note that the current binding is simply removed instead of being deprecated as it was only recently merged and would not allow for supporting DP mode. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-08-30dt-bindings: phy: Add PHY_TYPE_USXGMII definitionSwapnil Jakhade1-0/+1
Add definition for USXGMII phy type. Cc: Rob Herring <[email protected]> Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Roger Quadros <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-12-27dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clockSwapnil Jakhade1-0/+1
Add clock ID for Sierra derived reference clock. Signed-off-by: Swapnil Jakhade <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-12-27dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic namesSwapnil Jakhade1-4/+4
Rename SSC macros to use generic names instead of PHY specific names, so that they can be used to specify SSC modes for both Torrent and Sierra. Renaming the macros should not affect the things as these are not being used in any DTS file yet. Signed-off-by: Swapnil Jakhade <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-12-14dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phyRichard Zhu1-0/+14
Add binding for reference clock PAD modes of the i.MX8 PCIe PHY. Signed-off-by: Richard Zhu <[email protected]> Tested-by: Marcel Ziswiler <[email protected]> Reviewed-by: Tim Harvey <[email protected]> Tested-by: Tim Harvey <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-11-23dt-bindings: phy: Add constants for lan966x serdesHoratiu Vultur1-0/+14
Lan966x has: 2 integrated PHYs, 3 SerDes and 2 RGMII interfaces. Which requires to be muxed based on the HW representation. So add constants for each interface to be able to distinguish them. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Horatiu Vultur <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-10-26dt-bindings: phy: cadence-torrent: Add clock IDs for derived and received refclkSwapnil Jakhade1-0/+2
Add clock IDs for derived and received reference clock output. Signed-off-by: Swapnil Jakhade <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-08-07dt-bindings: msm: dsi: document phy-type property for 7nm dsi phyJonathan Marek1-0/+2
Document a new phy-type property which will be used to determine whether the phy should operate in D-PHY or C-PHY mode. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Rob Herring <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
2021-03-31dt-bindings: phy: phy-cadence-sierra: Add binding to model Sierra as clock ↵Kishon Vijay Abraham I1-0/+4
provider Add #clock-cells binding to model Sierra as clock provider and include clock IDs for PLL_CMNLC and PLL_CMNLC1. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-03-31phy: cadence-torrent: Use a common header file for Cadence SERDESKishon Vijay Abraham I1-4/+5
No functional change. In order to have a single header file for all Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is in preparation for adding Cadence Sierra SERDES specific macros. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Reviewed-by: Swapnil Jakhade <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-03-17dt-bindings: phy: cadence-torrent: Add binding for refclk driverKishon Vijay Abraham I1-0/+2
Add binding for refclk driver used to route the refclk out of torrent SERDES. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-03-17dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES WrapperKishon Vijay Abraham I1-0/+21
Add bindings for AM64 SERDES Wrapper. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-09-18dt-bindings: phy: Add PHY_TYPE_QSGMII definitionSwapnil Jakhade1-0/+1
Add definition for QSGMII phy type. Signed-off-by: Swapnil Jakhade <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-09-18dt-bindings: phy: cadence-torrent: Add binding to specify SSC modeSwapnil Jakhade1-0/+13
Add binding to specify Spread Spectrum Clocking mode used. Signed-off-by: Swapnil Jakhade <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-06-29dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHYAnurag Kumar Vulisha1-0/+1
Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed Processing System Gigabit Transceiver which provides PHY capabilities to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-05-19dt-bindings: phy: Add PHY_TYPE_XPCS definitionDilip Kota1-0/+1
Add definition for Ethernet PCS phy type. Signed-off-by: Dilip Kota <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-By: Vinod Koul <[email protected]> Link: https://lore.kernel.org/r/6091f0d2a1046f1e3656d9e33b6cc433d5465eaf.1589868358.git.eswara.kota@linux.intel.com Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-01-17dt-bindings: phy: Add PHY_TYPE_DP definitionJyri Sarha1-0/+1
Add definition for DisplayPort phy type. Signed-off-by: Jyri Sarha <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Reviewed-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2019-08-23dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYsMartin Blumenstingl1-0/+11
Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs. The IP block contains settings for the PHY and a PLL. The PLL mode is configurable through a dedicated #phy-cell in .dts. Signed-off-by: Martin Blumenstingl <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422Thomas Gleixner1-4/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 101 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Allison Randal <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194Thomas Gleixner1-1/+1
Based on 1 normalized pattern(s): license terms gnu general public license gpl version 2 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Allison Randal <[email protected]> Reviewed-by: Alexios Zavras <[email protected]> Reviewed-by: Steve Winslow <[email protected]> Reviewed-by: Richard Fontana <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-04-17dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoCKishon Vijay Abraham I1-0/+13
AM654x has two SERDES instances. Each instance has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The left and right input reference clock of SERDES0 and SERDES1 respectively are connected to the SoC clock. In the case of two lane SERDES personality card, the left input of SERDES1 is connected to the right output of SERDES0 in a chained fashion. See section "Reference Clock Distribution" of AM65x Sitara Processors TRM (SPRUID7 – April 2018) for more details. Add dt-binding documentation in order to represent all these different configurations in device tree. Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2018-10-22dt-bindings: phy: Update SERDES_MAX to be SERDES_MAX + 1Gustavo A. R. Silva1-1/+1
SERDES_MAX is a valid value to index ctrl->phys in drivers/phy/mscc/phy-ocelot-serdes.c. But, currently, there is an out-of-bounds bug in the mentioned driver when reading from ctrl->phys, because the size of array ctrl->phys is SERDES_MAX. Partially fix this by updating SERDES_MAX to be SERDES6G_MAX + 1. Notice that this is the first part of the solution to the out-of-bounds bug mentioned above. Although this change is not dependent on any other one. Suggested-by: Quentin Schulz <[email protected]> Reviewed-by: Quentin Schulz <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-10-05dt-bindings: add constants for Microsemi Ocelot SerDes driverQuentin Schulz1-0/+12
The Microsemi Ocelot has multiple SerDes and requires that the SerDes be muxed accordingly to the hardware representation. Let's add a constant for each SerDes available in the Microsemi Ocelot. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-05-20dt-bindings: phy-qcom-usb2: Add support to override tuning valuesManu Gautam1-0/+37
To improve eye diagram for PHYs on different boards of same SOC, some parameters may need to be changed. Provide device tree properties to override these from board specific device tree files. While at it, replace "qcom,qusb2-v2-phy" with compatible string for USB2 PHY on sdm845 which was earlier added for sdm845 only. Signed-off-by: Manu Gautam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2017-10-23dt-bindings: phy: Add PHY_TYPE_UFS definitionVivek Gautam1-0/+1
Add definition for UFS phy type. Signed-off-by: Vivek Gautam <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2015-06-21phy: Add binding document for Pistachio USB2.0 PHYAndrew Bresticker1-0/+16
Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC. Signed-off-by: Andrew Bresticker <[email protected]> Cc: Rob Herring <[email protected]> Cc: Pawel Moll <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Ian Campbell <[email protected]> Cc: Kumar Gala <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: James Hartley <[email protected]> Cc: Damien Horsley <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/9727/ Signed-off-by: Ralf Baechle <[email protected]>
2015-04-03phy: miphy365x: Use the generic phy type constants in dt-bindings/phy/phy.hPeter Griffin1-14/+0
Now there are generic phy type constants declared in phy.h, migrate over to using them rather than defining our own. This change has been done as one atomic commit to be bisectable. Note: The values of the defines are the same, so there is no ABI breakage with this patch. Signed-off-by: Peter Griffin <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Lee Jones <[email protected]> Acked-by: Maxime Coquelin <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2014-11-26phy: add support for USB cluster on the Armada 375 SoCGregory CLEMENT1-0/+1
The Armada 375 SoC comes with an USB2 host and device controller and an USB3 controller. The USB cluster control register allows to manage common features of both USB controllers. This commit adds a driver integrated in the generic PHY framework to control this USB cluster feature. Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Thomas Petazzoni <[email protected]> [ [email protected] : Made it to use the updated devm_phy_create API and soem cosmentic changes in Kconfig file.] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Acked-by: Jason Cooper <[email protected]>
2014-11-11phy: Add PHY header file for DT x Driver definesGabriel FERNANDEZ1-0/+18
This provides the shared header file which will be reference from both PHY driver and its associated Device Tree node(s). Signed-off-by: Gabriel Fernandez <[email protected]>
2014-07-22phy: miphy365x: Add MiPHY365x header file for DT x Driver definesLee Jones1-0/+14
This provides the shared header file which will be reference from both the MiPHY365x driver and its associated Device Tree node(s). Cc: Kishon Vijay Abraham I <[email protected]> Acked-by: Mark Rutland <[email protected]> Acked-by: Alexandre Torgue <[email protected]> Signed-off-by: Lee Jones <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
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