aboutsummaryrefslogtreecommitdiff
path: root/include/dt-bindings/clock/qcom,gcc-ipq4019.h
AgeCommit message (Collapse)AuthorFilesLines
2023-08-15dt-bindings: clock: qcom: ipq4019: add missing networking resetsRobert Marko1-0/+6
Add bindings for the missing networking resets found in IPQ4019 GCC. Signed-off-by: Robert Marko <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2016-12-21clk: qcom: ipq4019: Add the nodes for pcnocAbhishek Sahu1-0/+1
The current ipq4019 clock driver does not have the node for PCNOC so this patch adds and registers the PCNOC clock nodes. This PCNOC clock is critical and should not be turned off so setting CRITICAL flag also. Signed-off-by: Abhishek Sahu <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-12-21clk: qcom: ipq4019: Add the apss cpu pll divider clock nodeAbhishek Sahu1-0/+1
The current ipq4019 clock driver does not have support for all the frequency supported by APSS CPU. APSS CPU frequency is provided with APSS CPU PLL divider which divides down the VCO frequency. This divider is nonlinear and specific to IPQ4019 so the standard divider code cannot be used for this. Signed-off-by: Abhishek Sahu <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-12-21clk: qcom: ipq4019: remove fixed clocks and add pll clocksAbhishek Sahu1-0/+9
The current ipq4019 clock driver registered the PLL clocks and dividers as fixed clock. These fixed clock needs to be removed from driver probe function and same need to be registered with clock framework. These PLL clocks should be programmed only once and the same are being programmed already by the boot loader so the set rate operation is not required for these clocks. Only the rate can be calculated by clock operations in clock driver file so this patch adds the same. The PLL takes the reference clock from XO and generates the intermediate VCO frequency. This VCO frequency will be divided down by different PLL internal dividers. Some of the PLL internal dividers are fixed while other are programmable. Signed-off-by: Abhishek Sahu <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-02-25clk: qcom: Add IPQ4019 Global Clock Controller supportVaradarajan Narayanan1-0/+158
This patch adds support for the global clock controller found on the IPQ4019 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Pradeep Banavathi <[email protected]> Signed-off-by: Senthilkumar N L <[email protected]> Signed-off-by: Varadarajan Narayanan <[email protected]> Signed-off-by: Matthew McClintock <[email protected]> Acked-by: Andy Gross <[email protected]> [[email protected]: Drop 0x16024 enable_reg in crypto_ahb] Signed-off-by: Stephen Boyd <[email protected]>