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path: root/include/dt-bindings/clock/imx6ul-clock.h
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2023-01-31clk: imx6ul: add ethernet refclock mux supportOleksij Rempel1-1/+5
Add ethernet refclock mux support and set it to internal clock by default. This configuration will not affect existing boards. clock tree before this patch: fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, |- pll6_enet fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ after this patch: fec1 <- enet1_ref_sel(mux) <- enet1_ref_125m (gate) <- ... `--<> enet1_ref_pad |- pll6_enet fec2 <- enet2_ref_sel(mux) <- enet2_ref_125m (gate) <- ... `--<> enet2_ref_pad Signed-off-by: Oleksij Rempel <[email protected]> Acked-by: Lee Jones <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-01-31clk: imx6ul: fix enet1 gate configurationOleksij Rempel1-1/+2
According to the "i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root of PLL6. It is controlling ENET1 separately. So, instead of this picture (implementation before this patch): fec1 <- enet_ref (divider) <---------------------------, |- pll6_enet (gate) fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ we should have this one (after this patch): fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, |- pll6_enet fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ With this fix, the RMII reference clock will be turned off, after setting network interface down on each separate interface (ip l s dev eth0 down). Which was not working before, on system with both FECs enabled. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-5/+1
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Enrico Weigelt <[email protected]> Reviewed-by: Kate Stewart <[email protected]> Reviewed-by: Allison Randal <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-10-17clk: imx6ul: add mmdc1 ipg clockAnson Huang1-1/+2
i.MX6UL has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-06-29clk: imx6ul: add GPIO clock gatesAnson Huang1-1/+7
i.MX6UL has GPIO clock gates in CCM CCGR, add them into clock tree for clock management. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-06-29dt-bindings: clock: imx6ul: Do not change the clock definition orderFabio Estevam1-21/+19
Commit f5a4670de966 ("clk: imx: Add new clo01 and clo2 controlled by CCOSR") introduced the CLK_CLKO definitions, but didn't put them at the end of the list, which may cause dtb breakage when running an old dtb with a newer kernel. In order to avoid that, simply add the new CLK_CKO clock definitions at the end of the list. Fixes: f5a4670de966 ("clk: imx: Add new clo01 and clo2 controlled by CCOSR") Reported-by: Stefan Wahren <[email protected]> Signed-off-by: Fabio Estevam <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Stefan Agner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-05-15clk: imx: Add new clo01 and clo2 controlled by CCOSRMichael Trimarchi1-13/+20
osc->cko2_sel->cko2_podf->clk_cko2->clk_cko Example of usage to provide clock to the sgtl5000 codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6UL_CLK_OSC>; #sound-dai-cells = <0>; clocks = <&clks IMX6UL_CLK_CKO>; assigned-clocks = <&clks IMX6UL_CLK_CKO2_SEL>, <&clks IMX6UL_CLK_CKO2_PODF>, <&clks IMX6UL_CLK_CKO2>, <&clks IMX6UL_CLK_CKO>; assigned-clock-parents = <&clks IMX6UL_CLK_OSC>, <&clks IMX6UL_CLK_CKO2_SEL>, <&clks IMX6UL_CLK_CKO2_PODF>, <&clks IMX6UL_CLK_CKO2>; clock-names = "mclk"; wlf,shared-lrclk; Signed-off-by: Matteo Lisi <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]> Tested-by: Michael Trimarchi <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-11-15clk: imx: clk-imx6ul: add clk support for imx6ullBai Ping1-1/+14
imx6ull is the derived SoC from imx6ul Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Bai Ping <[email protected]> Signed-off-by: Peter Chen <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-02-28clk: imx: add kpp clock for i.MX6ULLothar Waßmann1-1/+2
Add the necessary clock to use the KPP interface on i.MX6UL. Signed-off-by: Lothar Waßmann <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-02-28clk: imx: whitespace cleanup; no functional changeLothar Waßmann1-73/+73
remove whitespace before TAB. Signed-off-by: Lothar Waßmann <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2015-07-14clk: imx: add imx6ul clk tree supportFrank Li1-0/+240
Add imx6ul clock driver support. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Bai Ping <[email protected]> Signed-off-by: Fugang Duan <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
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