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Add a definition for the FSI clock.
Signed-off-by: Eddie James <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add reset definitions of AST2600 I3C and MAC controllers. In the case of
the I3C reset, since there is no reset-line hardware available for
`ASPEED_RESET_I3C_DMA`, a new macro `ASPEED_RESET_I3C` with the same ID
is introduced to provide a more accurate representation of the hardware.
The old macro `ASPEED_RESET_I3C_DMA` is kept to provide backward
compatibility.
Signed-off-by: Dylan Hung <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The current "not part of a gate" is a little ambiguous. Expand this a
little to clarify the reference to the paired clock + reset control.
Signed-off-by: Jeremy Kerr <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Joel Stanley <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Tested-by: Joel Stanley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The current ast2600 clock definitions include entries for i3c6 and i3c7
devices, which don't exist: there are no clock control lines documented
for these, and only i3c devices 0 through 5 are present.
So, remove the definitions for I3C6 and I3C7. Although this is a
potential ABI-breaking change, there are no in-tree users of these, and
any references would be broken anyway, as the hardware doesn't exist.
This is a partial cherry-pick and rework of ed44b8cdfdb and 1a35eb926d7
from Aspeed's own tree, originally by Dylan Hung
<[email protected]>.
Reviewed-by: Joel Stanley <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Jeremy Kerr <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Joel Stanley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The ast2600 hardware has a top-level clock for all i3c controller
peripherals (then gated to each individual controller), so add a
top-level i3c clock line to control this.
This is a partial cherry-pick and rework of ed44b8cdfdb and 1a35eb926d7
from Aspeed's own tree, originally by Dylan Hung
<[email protected]>.
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Signed-off-by: Jeremy Kerr <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Joel Stanley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add HACE reset bit definition for AST2500/AST2600.
Signed-off-by: Neal Liu <[email protected]>
Signed-off-by: Johnny Huang <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Herbert Xu <[email protected]>
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The AST2600 has an explicit gate for the RMII RCLK for each of the four
MACs.
Signed-off-by: Andrew Jeffery <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
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The ast2600 is a new BMC SoC from ASPEED. It contains many more clocks
than the previous iterations, so support is broken out into it's own
driver.
Signed-off-by: Joel Stanley <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
[[email protected]: Mark arrays const]
Signed-off-by: Stephen Boyd <[email protected]>
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