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This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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On SH7709S, DMAC can be found at 0xa4000020 (as with most of
the other sh3 cpu subtypes).
Split out definition of DMAC base address from definitions of
DMTE irqs.
Signed-off-by: Steve Glendinning <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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drivers/char/pcmcia/synclink_cs.c:284:1: warning: "CCR3" redefined
In file included from include/asm/cache.h:13,
from include/asm/processor_32.h:15,
from include/asm/processor.h:60,
from include/linux/prefetch.h:14,
from include/linux/list.h:8,
from include/linux/module.h:9,
from drivers/char/pcmcia/synclink_cs.c:38:
include/asm/cpu/cache.h:38:1: warning: this is the location of the previous definition
Signed-off-by: Paul Mundt <[email protected]>
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This patch provides specific clock support for the SH7712.
Signed-off-by: Andrew Murray <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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With all of the different CPU types this was getting a but unwieldly.
Since sh64 is now integrated, we don't have to worry about multiple
architectures caring about the header definitions.
Split out the defs for each asm/cpu/ to make rtc-sh slightly less
visually offensive.
Signed-off-by: Paul Mundt <[email protected]>
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Signed-off-by: Paul Mundt <[email protected]>
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The CPU family abstraction already exists, so move out the PXSEG
definition for each one. SH-2A already has this special cased,
and SH-5 will as well.
Signed-off-by: Paul Mundt <[email protected]>
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Signed-off-by: Jiri Olsa <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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Trivial build fixes for SH7709.
Signed-off-by: Kristoffer Ericson <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This adds support for the SH7720 (SH3-DSP) CPU.
Signed-off by: Markus Brunner <[email protected]>
Signed-off by: Mark Jonas <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This adds the PFC definitions for SH-3, as well as consolidating the
gpio.h mess within sh-sci. Stub in sh64, as it's the odd one out
between the sh-sci architectures (sh, sh64, h8300) in this capacity.
Signed-off by: Markus Brunner <[email protected]>
Signed-off by: Mark Jonas <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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This patch removes old dead code:
- kill off sh7300 cpu support
- get rid of broken solution engine 7300 board support
Signed-off-by: Magnus Damm <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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With the TMU register definitions being renamed on SH-4, SH-3 ended up
breaking. Update the TSTR define to match the SH-4 convention.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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There is no such thing as labeling a variable as __attribute__((used)). Since
ts_shift is not referenced in inline assembly, we assume that we're simply
suppressing a warning here if the variable is declared but unreferenced.
Cc: Paul Mundt <[email protected]>
Signed-off-by: David Rientjes <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
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Support the SH7712 (SH3-DSP) Solution Engine reference board.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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These ended up causing too many problems on older parts,
revert for now..
Signed-off-by: Paul Mundt <[email protected]>
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This converts the lazy dcache handling to the model described in
Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks
used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a
bonus, this slightly cuts down on the cache flushing frequency.
With that and the PTEA handling out of the way, the update_mmu_cache()
implementations can be consolidated, and we no longer have to worry
about which configuration the cache is in for the SH7705 case.
And finally, explicitly disable the lazy writeback on SMP (SH-4A).
Signed-off-by: Paul Mundt <[email protected]>
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Virtually index, physically tagged cache architectures can get away
without cache flushing when forking. This patch adds a new cache
flushing function flush_cache_dup_mm(struct mm_struct *) which for the
moment I've implemented to do the same thing on all architectures
except on MIPS where it's a no-op.
Signed-off-by: Ralf Baechle <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
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Some old rtc and io headers were left hanging around, kill them off..
Signed-off-by: Paul Mundt <[email protected]>
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Set the SHM alignment at runtime, based off of probed cache desc.
Optimize get_unmapped_area() to only colour align shared mappings.
Signed-off-by: Paul Mundt <[email protected]>
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This adds support for the aforementioned CPU subtypes, and cleans
up some build issues encountered as a result.
Signed-off-by: Paul Mundt <[email protected]>
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This adds some simple PM stubs and the basic APM interfaces,
primarily for use by hp6xx, where the existing userland
expects it.
Signed-off-by: Andriy Skulysh <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>
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We need this set to something sensible anywhere were we have
an aliasing dcache..
Signed-off-by: Paul Mundt <[email protected]>
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Cleanup of page table allocators, using generic folded PMD and PUD
helpers. TLB flushing operations are moved to a more sensible spot.
The page fault handler is also optimized slightly, we no longer waste
cycles on IRQ disabling for flushing of the page from the ITLB, since
we're already under CLI protection by the initial exception handler.
Signed-off-by: Paul Mundt <[email protected]>
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SH7300 has a different TMU_TOCR, make the TMU code work again.
Signed-off-by: Paul Mundt <[email protected]>
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Currently entry.S is home to these definitions, so we move them somewhere more
sensible. IPR IRQ handling depends on being to read from INTEVT.
Signed-off-by: Paul Mundt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
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This extends the current SH DMA API somewhat to support a proper virtual
channel abstraction, and also works to represent this through the driver model
by giving each DMAC its own platform device.
There's also a few other minor changes to support a few new CPU subtypes, and
make TEI generation for the SH DMAC configurable.
Signed-off-by: Paul Mundt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
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Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
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