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path: root/drivers/usb/dwc3/dwc3-pci.c
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2024-07-03usb: dwc3: pci: add support for the Intel Panther LakeHeikki Krogerus1-0/+8
This patch adds the necessary PCI IDs for Intel Panther Lake devices. Signed-off-by: Heikki Krogerus <[email protected]> Cc: stable <[email protected]> Acked-by: Thinh Nguyen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-04-09usb: dwc3: pci: Don't set "linux,phy_charger_detect" property on Lenovo Yoga ↵Hans de Goede1-1/+7
Tab2 1380 The Lenovo Yoga Tablet 2 Pro 1380 model is the exception to the rule that devices which use the Crystal Cove PMIC without using ACPI for battery and AC power_supply class support use the USB-phy for charger detection. Unlike the Lenovo Yoga Tablet 2 830 / 1050 models this model has an extra LC824206XA Micro USB switch which does the charger detection. Add a DMI quirk to not set the "linux,phy_charger_detect" property on the 1380 model. This quirk matches on the BIOS version to differentiate the 1380 model from the 830 and 1050 models which otherwise have the same DMI strings. Signed-off-by: Hans de Goede <[email protected]> Acked-by: Thinh Nguyen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-03-26usb: dwc3: pci: Drop duplicate IDHeikki Krogerus1-2/+0
Intel Arrow Lake CPU uses the Meteor Lake ID with this controller (the controller that's part of the Intel Arrow Lake chipset (PCH) does still have unique PCI ID). Fixes: de4b5b28c87c ("usb: dwc3: pci: add support for the Intel Arrow Lake-H") Signed-off-by: Heikki Krogerus <[email protected]> Acked-by: Thinh Nguyen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-01-27usb: dwc3: pci: add support for the Intel Arrow Lake-HHeikki Krogerus1-0/+4
This patch adds the necessary PCI ID for Intel Arrow Lake-H devices. Acked-by: Thinh Nguyen <[email protected]> Signed-off-by: Heikki Krogerus <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-07-27usb: dwc3: pci: skip BYT GPIO lookup table for hardwired phyGratian Crisan1-2/+4
Hardware based on the Bay Trail / BYT SoCs require an external ULPI phy for USB device-mode. The phy chip usually has its 'reset' and 'chip select' lines connected to GPIOs described by ACPI fwnodes in the DSDT table. Because of hardware with missing ACPI resources for the 'reset' and 'chip select' GPIOs commit 5741022cbdf3 ("usb: dwc3: pci: Add GPIO lookup table on platforms without ACPI GPIO resources") introduced a fallback gpiod_lookup_table with hard-coded mappings for Bay Trail devices. However there are existing Bay Trail based devices, like the National Instruments cRIO-903x series, where the phy chip has its 'reset' and 'chip-select' lines always asserted in hardware via resistor pull-ups. On this hardware the phy chip is always enabled and the ACPI dsdt table is missing information not only for the 'chip-select' and 'reset' lines but also for the BYT GPIO controller itself "INT33FC". With the introduction of the gpiod_lookup_table initializing the USB device-mode on these hardware now errors out. The error comes from the gpiod_get_optional() calls in dwc3_pci_quirks() which will now return an -ENOENT error due to the missing ACPI entry for the INT33FC gpio controller used in the aforementioned table. This hardware used to work before because gpiod_get_optional() will return NULL instead of -ENOENT if no GPIO has been assigned to the requested function. The dwc3_pci_quirks() code for setting the 'cs' and 'reset' GPIOs was then skipped (due to the NULL return). This is the correct behavior in cases where the phy chip is hardwired and there are no GPIOs to control. Since the gpiod_lookup_table relies on the presence of INT33FC fwnode in ACPI tables only add the table if we know the entry for the INT33FC gpio controller is present. This allows Bay Trail based devices with hardwired dwc3 ULPI phys to continue working. Fixes: 5741022cbdf3 ("usb: dwc3: pci: Add GPIO lookup table on platforms without ACPI GPIO resources") Cc: stable <[email protected]> Signed-off-by: Gratian Crisan <[email protected]> Reviewed-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-04-10Merge 6.3-rc6 into usb-nextGreg Kroah-Hartman1-0/+2
We need the USB fixes in here for testing, and this resolves two merge conflicts, one pointed out by linux-next: drivers/usb/dwc3/dwc3-pci.c drivers/usb/host/xhci-pci.c Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-04-05usb: dwc3: pci: add support for the Intel Meteor Lake-SHeikki Krogerus1-0/+4
This patch adds the necessary PCI ID for Intel Meteor Lake-S devices. Signed-off-by: Heikki Krogerus <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-04-05usb: dwc3: pci: Change PCI device macrosAndy Shevchenko1-98/+34
Use PCI_DEVICE_DATA() macro. No functional changes are expected. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-02-15usb: dwc3: pci: add support for the Intel Meteor Lake-MHeikki Krogerus1-0/+4
This patch adds the necessary PCI IDs for Intel Meteor Lake-M devices. Signed-off-by: Heikki Krogerus <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-11-29usb: dwc3: pci: Update PCIe device ID for USB3 controller on CPU sub-system ↵Shruthi Sanil1-1/+1
for Raptor Lake The device ID 0xa70e is defined for the USB3 device controller in the CPU sub-system of Raptor Lake platform. Hence updating the ID accordingly. Fixes: bad0d1d726ac ("usb: dwc3: pci: Add support for Intel Raptor Lake") Cc: stable <[email protected]> Reviewed-by: Heikki Krogerus <[email protected]> Signed-off-by: Shruthi Sanil <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-09-22usb: dwc3: pci: Add PCIe device ID for USB3 controller on CPU sub-system for ↵Shruthi Sanil1-0/+4
Alder Lake P USB3 PCIe device ID's needs to be updated for the device to enumerate as a USB3 device on the host for Alder Lake P. Reviewed-by: Heikki Krogerus <[email protected]> Signed-off-by: Shruthi Sanil <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-09-22usb: dwc3: pci: Update the macro names for USB PCIe device ID's for Alder ↵Shruthi Sanil1-6/+6
Lake platforms The device ID 0x465e is defined for the USB3 device controller in the CPU sub-system of Alder Lake N platform. Hence updating the macro name accordingly. The device ID 0x54ee is defined for the USB2 controller on the PCH sub-system for Alder Lake N platform. Hence updating the macro name accordingly. The device ID's defined for Alder Lake P is shared between Alder Lake P, Alder Lake PS and Alder Lake M. Hence updating the macro name to ADL from ADLP to make it common and keeping it aligned with the xHCI ID's naming convention. As we have two device controllers on Alder Lake platforms i.e. one on PCH sub-system and another on CPU sub-system(USB3), appending _PCH for the USB2 device ID macro to differentiate between the 2 ID's. Reviewed-by: Heikki Krogerus <[email protected]> Signed-off-by: Shruthi Sanil <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-08-18usb: dwc3: pci: Add support for Intel Raptor LakeHeikki Krogerus1-0/+4
This adds the necessary PCI device ID for the controller inside the Intel Raptor Lake CPU block. The controllers that are part of the PCH (chipset) have separate device IDs. Cc: [email protected] Signed-off-by: Heikki Krogerus <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-06-10usb: dwc3: pci: Restore line lost in merge conflict resolutionStephan Gerhold1-0/+1
Commit 582ab24e096f ("usb: dwc3: pci: Set "linux,phy_charger_detect" property on some Bay Trail boards") added a new swnode similar to the existing ones for boards where the PHY handles charger detection. Unfortunately, the "linux,sysdev_is_parent" property got lost in the merge conflict resolution of commit ca9400ef7f67 ("Merge 5.17-rc6 into usb-next"). Now dwc3_pci_intel_phy_charger_detect_properties is the only swnode in dwc3-pci that is missing "linux,sysdev_is_parent". It does not seem to cause any obvious functional issues, but it's certainly unintended so restore the line to make the properties consistent again. Fixes: ca9400ef7f67 ("Merge 5.17-rc6 into usb-next") Cc: [email protected] Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-05-03Merge 5.18-rc5 into usb-nextGreg Kroah-Hartman1-0/+8
We need the USB fixes in here, and this resolves a merge issue in drivers/usb/dwc3/drd.c Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-04-26usb: dwc3: pci: add support for the Intel Meteor Lake-PHeikki Krogerus1-0/+8
This patch adds the necessary PCI IDs for Intel Meteor Lake-P devices. Signed-off-by: Heikki Krogerus <[email protected]> Cc: stable <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-04-23usb: dwc3: pci: Fix pm_runtime_get_sync() error checkingZheng Yongjun1-1/+1
If the device is already in a runtime PM enabled state pm_runtime_get_sync() will return 1, so a test for negative value should be used to check for errors. Fixes: 8eed00b237a28 ("usb: dwc3: pci: Runtime resume child device from wq") Signed-off-by: Zheng Yongjun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-03-15usb: dwc3: pci: Add support for Intel Alder LakeShruthi Sanil1-0/+4
Add the PCI device ID and update the dwc3_pci_id_table for Intel Alder Lake SoC. The DWC3 controllor in the CPU block handles the USB3 traffic and the device ID is common across the Alder Lake platforms. Reviewed-by: Heikki Krogerus <[email protected]> Signed-off-by: Shruthi Sanil <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-02-28Merge 5.17-rc6 into usb-nextGreg Kroah-Hartman1-3/+17
We need the USB fixes in here, and it resolves a merge conflict in: drivers/usb/dwc3/dwc3-pci.c Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-02-17usb: dwc3: pci: Also apply Bay Trail GPIO mappings to ulpi-deviceHans de Goede1-0/+8
In order for the phy driver to be able to actually get and control the cs and reset GPIOs the dev_id member of the gpiod_lookup table must be set to point to the dev_name() of the ulpi-device instantiated by dwc3_ulpi_init(). Signed-off-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-02-17usb: dwc3: pci: Set "linux,phy_charger_detect" property on some Bay Trail boardsHans de Goede1-0/+24
Some Android x86 tablets with a Bay Trail (BYT) SoC and a Crystal Cove PMIC, which does not support charger-detection, rely on the TUSB1211 phy for charger-detection. Windows tablets with the same SoC + PMIC often use an extra chip for charger-detection like the FSA831A. But since on Android tablets the designers already need to add a TUSB1211 phy to support device/gadget mode the phy is used to do charger-detection instead. These Android x86 tablets can be identified by the unique combination of a Bay Trail SoC (already checked for by PCI-ids) + a Crystal Cove PMIC + not using the standard ACPI battery and ac drivers. Where as on Windows tablets the standard ACPI battery and ac drivers will be used on BYT boards with a Crystal Cove PMIC. Set a special kernel-internal (so not part of the dt-bindings) "linux,phy_charger_detect" property on these boards, which tells the tusb1210 driver to enable charger-detection. Signed-off-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-02-17usb: dwc3: pci: Set the swnode from inside dwc3_pci_quirks()Hans de Goede1-7/+4
The quirk handling may need to set some different properties which means using a different swnode, move the setting of the swnode to inside dwc3_pci_quirks() so that the quirk handling can choose a different swnode. Signed-off-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-02-17usb: dwc3: pci: Fix Bay Trail phy GPIO mappingsHans de Goede1-2/+2
When the Bay Trail phy GPIO mappings where added cs and reset were swapped, this did not cause any issues sofar, because sofar they were always driven high/low at the same time. Note the new mapping has been verified both in /sys/kernel/debug/gpio output on Android factory images on multiple devices, as well as in the schematics for some devices. Fixes: 5741022cbdf3 ("usb: dwc3: pci: Add GPIO lookup table on platforms without ACPI GPIO resources") Cc: stable <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-02-15usb: dwc3: pci: Add "snps,dis_u2_susphy_quirk" for Intel Bay TrailHans de Goede1-1/+12
Commit e0082698b689 ("usb: dwc3: ulpi: conditionally resume ULPI PHY") fixed an issue where ULPI transfers would timeout if any requests where send to the phy sometime after init, giving it enough time to auto-suspend. Commit e5f4ca3fce90 ("usb: dwc3: ulpi: Fix USB2.0 HS/FS/LS PHY suspend regression") changed the behavior to instead of clearing the DWC3_GUSB2PHYCFG_SUSPHY bit, add an extra sleep when it is set. But on Bay Trail devices, when phy_set_mode() gets called during init, this leads to errors like these: [ 28.451522] tusb1210 dwc3.ulpi: error -110 writing val 0x01 to reg 0x0a [ 28.464089] tusb1210 dwc3.ulpi: error -110 writing val 0x01 to reg 0x0a Add "snps,dis_u2_susphy_quirk" to the settings for Bay Trail devices to fix this. This restores the old behavior for Bay Trail devices, since previously the DWC3_GUSB2PHYCFG_SUSPHY bit would get cleared on the first ulpi_read/_write() and then was never set again. Fixes: e5f4ca3fce90 ("usb: dwc3: ulpi: Fix USB2.0 HS/FS/LS PHY suspend regression") Cc: [email protected] Cc: Serge Semin <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-02-15usb: dwc3: pci: add support for the Intel Raptor Lake-SHeikki Krogerus1-0/+4
This patch adds the necessary PCI ID for Intel Raptor Lake-S devices. Signed-off-by: Heikki Krogerus <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-08-26usb: dwc3: pci: add support for AMD's newer generation platform.Nehal Bakulchandra Shah1-0/+17
AMD's latest platforms has DWC3 controller. Add the PCI ID and properties for the same. Signed-off-by: Nehal Bakulchandra Shah <[email protected]> Acked-by: Felipe Balbi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-05-17Merge 5.13-rc2 into usb-nextGreg Kroah-Hartman1-0/+1
We need the USB fixes in here as well. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-05-13usb: dwc3: pci: Fix DEFINE for Intel Elkhart LakeRaymond Tan1-4/+4
There's no separate low power (LP) version of Elkhart Lake, thus this patch updates the PCI Device ID DEFINE to indicate this. Acked-by: Felipe Balbi <[email protected]> Signed-off-by: Raymond Tan <[email protected]> Signed-off-by: Heikki Krogerus <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-05-10usb: dwc3: pci: Enable usb2-gadget-lpm-disable for Intel MerrifieldFerry Toth1-0/+1
On Intel Merrifield LPM is causing host to reset port after a timeout. By disabling LPM entirely this is prevented. Fixes: 066c09593454 ("usb: dwc3: pci: Enable extcon driver for Intel Merrifield") Reviewed-by: Andy Shevchenko <[email protected]> Signed-off-by: Ferry Toth <[email protected]> Cc: stable <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-04-09usb: dwc3: pci: add support for the Intel Alder Lake-MHeikki Krogerus1-0/+4
This patch adds the necessary PCI ID for Intel Alder Lake-M devices. Signed-off-by: Heikki Krogerus <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-04-05Merge 5.12-rc6 into usb-nextGreg Kroah-Hartman1-0/+2
We want the USB fixes in here as well and it resolves a merge issue with xhci-mtk.c Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-04-02usb: dwc3: fix incorrect kernel-doc comment syntax in filesAditya Srivastava1-1/+1
The opening comment mark '/**' is used for highlighting the beginning of kernel-doc comments. There are certain files in drivers/usb/dwc3, which follow this syntax, but the content inside does not comply with kernel-doc. Such lines were probably not meant for kernel-doc parsing, but are parsed due to the presence of kernel-doc like comment syntax(i.e, '/**'), which causes unexpected warnings from kernel-doc. E.g., presence of kernel-doc like comment in drivers/usb/dwc3/io.h at header causes this warnings by kernel-doc: "warning: expecting prototype for h(). Prototype was for __DRIVERS_USB_DWC3_IO_H() instead" Similarly for other files too. Provide a simple fix by replacing such occurrences with general comment format, i.e. '/*', to prevent kernel-doc from parsing it. Acked-by: Randy Dunlap <[email protected]> Signed-off-by: Aditya Srivastava <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-03-23usb: dwc3: pci: Enable dis_uX_susphy_quirk for Intel MerrifieldAndy Shevchenko1-0/+2
It seems that on Intel Merrifield platform the USB PHY shouldn't be suspended. Otherwise it can't be enabled by simply change the cable in the connector. Enable corresponding quirk for the platform in question. Fixes: e5f4ca3fce90 ("usb: dwc3: ulpi: Fix USB2.0 HS/FS/LS PHY suspend regression") Suggested-by: Serge Semin <[email protected]> Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-01-15usb: dwc3: pci: add support for the Intel Alder Lake-PHeikki Krogerus1-0/+4
This patch adds the necessary PCI ID for Intel Alder Lake-P devices. Acked-by: Felipe Balbi <[email protected]> Signed-off-by: Heikki Krogerus <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-01-15usb: dwc3: pci: ID for Tiger Lake CPUHeikki Krogerus1-0/+4
Tiger Lake SOC (the versions of it that have integrated USB4 controller) may have two DWC3 controllers. One is part of the PCH (Platform Controller Hub, i.e. the chipset) as usual, and the other is inside the actual CPU block. On all Intel platforms that have the two separate DWC3 controllers, the one inside the CPU handles USB3 and only USB3 traffic, while the PCH version handles USB2 and USB2 alone. The reason for splitting the two busses like this is to allow easy USB3 tunneling over USB4 connections. As USB2 is not tunneled over USB4, it has dedicated USB controllers (both xHCI and DWC3). Acked-by: Felipe Balbi <[email protected]> Signed-off-by: Heikki Krogerus <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-01-15usb: dwc3: pci: Register a software node for the dwc3 platform deviceHeikki Krogerus1-24/+37
By registering the software node directly instead of just the properties in it, the driver can take advantage of also the other features the software nodes have. Acked-by: Felipe Balbi <[email protected]> Signed-off-by: Heikki Krogerus <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-10-27usb: dwc3: pci: add support for the Intel Alder Lake-SHeikki Krogerus1-0/+4
This patch adds the necessary PCI ID for Intel Alder Lake-S devices. Signed-off-by: Heikki Krogerus <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-10-02usb: dwc3: pci: Allow Elkhart Lake to utilize DSM method for PM functionalityRaymond Tan1-1/+2
Similar to some other IA platforms, Elkhart Lake too depends on the PMU register write to request transition of Dx power state. Thus, we add the PCI_DEVICE_ID_INTEL_EHLLP to the list of devices that shall execute the ACPI _DSM method during D0/D3 sequence. [[email protected]: included Fixes tag] Fixes: dbb0569de852 ("usb: dwc3: pci: Add Support for Intel Elkhart Lake Devices") Cc: [email protected] Signed-off-by: Raymond Tan <[email protected]> Signed-off-by: Heikki Krogerus <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-07-20Merge 5.8-rc6 into usb-nextGreg Kroah-Hartman1-0/+8
We need the USB fixes in here as well. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-07-15usb: dwc3: Replace HTTP links with HTTPS onesAlexander A. Klimov1-1/+1
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-07-09usb: dwc3: pci: add support for the Intel Jasper LakeHeikki Krogerus1-0/+4
This patch adds the necessary PCI ID for Intel Jasper Lake devices. Signed-off-by: Heikki Krogerus <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-07-09usb: dwc3: pci: add support for the Intel Tiger Lake PCH -H variantHeikki Krogerus1-0/+4
This patch adds the necessary PCI ID for TGP-H devices. Signed-off-by: Heikki Krogerus <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-06-24usb: dwc3: pci: Fix reference count leak in dwc3_pci_resume_workAditya Pakki1-1/+3
dwc3_pci_resume_work() calls pm_runtime_get_sync() that increments the reference counter. In case of failure, decrement the reference before returning. Signed-off-by: Aditya Pakki <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-05-09usb: dwc3: pci: Enable extcon driver for Intel MerrifieldAndy Shevchenko1-0/+1
Intel Merrifield provides a DR support via PMIC which has its own extcon driver. Add a property string to link to that driver. Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-01-22usb: dwc3: pci: add ID for the Intel Comet Lake -V variantHeikki Krogerus1-0/+4
There is one more Comet Lake PCH variant, CML-V, that has its own PCI ID. Signed-off-by: Heikki Krogerus <[email protected]> Cc: stable <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-12-12usb: dwc3: pci: add ID for the Intel Comet Lake -H variantHeikki Krogerus1-1/+5
The original ID that was added for Comet Lake PCH was actually for the -LP (low power) variant even though the constant for it said CMLH. Changing that while at it. Signed-off-by: Heikki Krogerus <[email protected]> Acked-by: Felipe Balbi <[email protected]> Cc: stable <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-10-27usb: dwc3: pci: prevent memory leak in dwc3_pci_probeNavid Emamdoost1-1/+1
In dwc3_pci_probe a call to platform_device_alloc allocates a device which is correctly put in case of error except one case: when the call to platform_device_add_properties fails it directly returns instead of going to error handling. This commit replaces return with the goto. Fixes: 1a7b12f69a94 ("usb: dwc3: pci: Supply device properties via driver data") Signed-off-by: Navid Emamdoost <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-07-03usb: dwc3: pci: add support for TigerLake DevicesFelipe Balbi1-0/+4
This patch adds the necessary PCI ID for TGP-LP devices. Signed-off-by: Felipe Balbi <[email protected]>
2019-06-20usb: dwc3: pci: Add Support for Intel Elkhart Lake DevicesFelipe Balbi1-0/+4
This patch simply adds a new PCI Device ID Signed-off-by: Felipe Balbi <[email protected]>
2019-03-20usb: dwc3: pci: add support for Comet Lake PCH IDFelipe Balbi1-0/+4
This patch simply adds a new PCI Device ID Signed-off-by: Felipe Balbi <[email protected]>