aboutsummaryrefslogtreecommitdiff
path: root/drivers/usb/dwc2/params.c
AgeCommit message (Collapse)AuthorFilesLines
2024-10-29Revert "usb: dwc2: Skip clock gating on Broadcom SoCs"Stefan Wahren1-1/+0
The commit d483f034f032 ("usb: dwc2: Skip clock gating on Broadcom SoCs") introduced a regression on Raspberry Pi 3 B Plus, which prevents enumeration of the onboard Microchip LAN7800 in case no external USB device is connected during boot. Fixes: d483f034f032 ("usb: dwc2: Skip clock gating on Broadcom SoCs") Signed-off-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-07-31usb: dwc2: Skip clock gating on Broadcom SoCsStefan Wahren1-0/+1
On resume of the Raspberry Pi the dwc2 driver fails to enable HCD_FLAG_HW_ACCESSIBLE before re-enabling the interrupts. This causes a situation where both handler ignore a incoming port interrupt and force the upper layers to disable the dwc2 interrupt line. This leaves the USB interface in a unusable state: irq 66: nobody cared (try booting with the "irqpoll" option) CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 6.10.0-rc3 Hardware name: BCM2835 Call trace: unwind_backtrace from show_stack+0x10/0x14 show_stack from dump_stack_lvl+0x50/0x64 dump_stack_lvl from __report_bad_irq+0x38/0xc0 __report_bad_irq from note_interrupt+0x2ac/0x2f4 note_interrupt from handle_irq_event+0x88/0x8c handle_irq_event from handle_level_irq+0xb4/0x1ac handle_level_irq from generic_handle_domain_irq+0x24/0x34 generic_handle_domain_irq from bcm2836_chained_handle_irq+0x24/0x28 bcm2836_chained_handle_irq from generic_handle_domain_irq+0x24/0x34 generic_handle_domain_irq from generic_handle_arch_irq+0x34/0x44 generic_handle_arch_irq from __irq_svc+0x88/0xb0 Exception stack(0xc1b01f20 to 0xc1b01f68) 1f20: 0005c0d4 00000001 00000000 00000000 c1b09780 c1d6b32c c1b04e54 c1a5eae8 1f40: c1b04e90 00000000 00000000 00000000 c1d6a8a0 c1b01f70 c11d2da8 c11d4160 1f60: 60000013 ffffffff __irq_svc from default_idle_call+0x1c/0xb0 default_idle_call from do_idle+0x21c/0x284 do_idle from cpu_startup_entry+0x28/0x2c cpu_startup_entry from kernel_init+0x0/0x12c handlers: [<f539e0f4>] dwc2_handle_common_intr [<75cd278b>] usb_hcd_irq Disabling IRQ #66 Disabling clock gating workaround this issue. Fixes: 0112b7ce68ea ("usb: dwc2: Update dwc2_handle_usb_suspend_intr function.") Link: https://lore.kernel.org/linux-usb/[email protected]/T/ Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Stefan Wahren <[email protected]> Acked-by: Minas Harutyunyan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-07-31usb: dwc2: Add comment about BCM2848 ACPI IDStefan Wahren1-0/+1
During recent code review the different naming between ACPI and OF IDs led to confusion. So add a clarifying comment. Link: https://lore.kernel.org/linux-usb/[email protected]/ Signed-off-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-07-10usb: dwc2: add support for other Lantiq SoCsHauke Mehrtens1-5/+25
The size of the internal RAM of the DesignWare USB controller changed between the different Lantiq SoCs. We have the following sizes: Amazon + Danube: 8 KByte Amazon SE + arx100: 2 KByte xrx200 + xrx300: 2.5 KByte For Danube SoC we do not provide the params and let the driver decide to use sane defaults, for the Amazon SE and arx100 we use small fifos and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo. The auto detection of max_transfer_size and max_packet_count should work, so remove it. This patch is included in OpenWrt for many years. Signed-off-by: Hauke Mehrtens <[email protected]> Acked-by: Minas Harutyunyan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-03-27usb: dwc2: add support for Sophgo CV18XX/SG200X series SoCInochi Amaoto1-0/+21
Add params for DWC2 IP in Sophgo CV18XX/SG200X series SoC. Signed-off-by: Inochi Amaoto <[email protected]> Acked-by: Minas Harutyunyan <[email protected]> Link: https://lore.kernel.org/r/IA1PR20MB4953EE73DD36D5FFC81D90EDBB352@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-03-26usb: dwc2: Add new parameter eusb2_discMinas Harutyunyan1-0/+22
Added new parameter eusb2_disc to list of core parameters which specify whether eUSB2 PHY disconnect support flow applicable or no. Set to false as default value and checked core version if set to true. This parameter applicable in device mode of HSOTG and HS IOT cores v5.00 or higher. Added print this parameter in show parameters of debugfs. Signed-off-by: Minas Harutyunyan <[email protected]> Link: https://lore.kernel.org/r/e77cc4312bda797d1ddaa4351d86c65a69c8b926.1708948356.git.Minas.Harutyunyan@synopsys.com Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-01-02usb: dwc2: Disable clock gating feature on Rockchip SoCsWilliam Wu1-0/+1
The DWC2 IP on the Rockchip SoCs doesn't support clock gating. When a clock gating is enabled, system hangs. Signed-off-by: William Wu <[email protected]> Acked-by: Minas Harutyunyan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-10-10usb: Use device_get_match_data()Rob Herring1-15/+6
Use preferred device_get_match_data() instead of of_match_device() to get the driver match data. With this, adjust the includes to explicitly include the correct headers. Signed-off-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-08-22usb: dwc2: add pci_device_id driver_data parse supportYinbo Zhu1-1/+38
The dwc2 driver has everything we need to run in PCI mode except for pci_device_id driver_data parse. With that to set Loongson dwc2 element and added identified as PCI_VENDOR_ID_LOONGSON and PCI_DEVICE_ID_LOONGSON_DWC2 in dwc2_pci_ids, the Loongson dwc2 controller will work. Signed-off-by: Yinbo Zhu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-05-13usb: dwc2: support dwc2 IP for Amlogic A1 SoC familyDmitry Rokosov1-0/+21
The Amlogic A1 uses dwc2 Synopsys IP as its USB peripheral (gadget) endpoint, with different DWC2 parameters when compared to previous Amlogic SoCs. Signed-off-by: Dmitry Rokosov <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Acked-by: Minas Harutyunyan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-03-16usb: Use of_property_read_bool() for boolean propertiesRob Herring1-2/+1
It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. Convert reading boolean properties to to of_property_read_bool(). Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Richard Leitner <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-12-08usb: dwc2: disable lpm feature on Rockchip SoCsQuentin Schulz1-0/+4
LPM feature of DWC2 module integrated in Rockchip SoCs doesn't work properly or needs some additional handling, so disable it for now. Without disabling LPM feature, the USB ADB communication fail with the following error log: dwc2 ff580000.usb: new address 27 dwc2 ff580000.usb: Failed to exit L1 sleep state in 200us. dwc2 ff580000.usb: dwc2_hsotg_send_reply: cannot queue req dwc2 ff580000.usb: dwc2_hsotg_process_req_status: failed to send reply dwc2 ff580000.usb: dwc2_hsotg_enqueue_setup: failed queue (-11) dwc2 ff580000.usb: Failed to exit L1 sleep state in 200us. [diff vs vendor kernel: added lpm_clock_gating, besl and hird_threshold_en settings as seen in commit 53febc956900 ("usb: dwc2: disable Link Power Management on STM32MP15 HS OTG")] Signed-off-by: William Wu <[email protected]> Signed-off-by: Frank Wang <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Link: https://lore.kernel.org/r/20221206-dwc2-gadget-dual-role-v1-1-36515e1092cd@theobroma-systems.com Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-09-22usb: dwc2: Remove redundant license textChristophe JAILLET1-30/+0
SPDX-License-Identifier have been added in commit 5fd54ace4721 ("USB: add SPDX identifiers to all remaining files in drivers/usb/") There is no point in keeping the now redundant license text. Remove it. Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Link: https://lore.kernel.org/r/030a7e187d707f8734a492cda7a6b54d459c4bb3.1662788747.git.christophe.jaillet@wanadoo.fr Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-04-21USB: dwc2: Add OTG support for Ingenic SoCs.周琰杰 (Zhou Yanjie)1-1/+49
Add OTG support for the JZ4775 SoC, the JZ4780 SoC, the X1000 SoC, the X1600 SoC, the X1700 SoC, the X1830 SoC, and the X2000 SoC from Ingenic. Introduce support for disable Ingenic overcurrent detection, once selected, it enables the GOTGCTL register bits VbvalidOvEn and VbvalidOvVal to disable the VBUS overcurrent detection. This patch is derived from Dragan Čečavac (in the kernel 3.18.3 tree of CI20). It is very useful for the MIPS Creator CI20 (r1). Without this patch, OTG port of CI20 has a great probability to face overcurrent warning, which breaks the OTG functionality. Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Dragan Čečavac <[email protected]> Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2022-02-11usb: dwc2: Add platform specific data for Intel's AgilexDinh Nguyen1-0/+10
The DWC2 IP on the Agilex platform does not support clock-gating. Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-10-25usb: dwc2: stm32mp15: set otg_revFabrice Gasnier1-0/+2
STM32MP15 complies with the OTG 2.0. Set OTG revision accordingly. It is useful for the of_usb_update_otg_caps() routine to check and update otg_rev to the lower value between DT and provided params. Signed-off-by: Fabrice Gasnier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-10-25usb: dwc2: add otg_rev and otg_caps information for gadget driverFabrice Gasnier1-33/+40
Currently the dwc2 doesn't fill in the 'otg_caps' of usb_gadget structure. When registering a gadget device (e.g. via configfs), the usb_otg_descriptor_init() checks the 'otg_caps' and 'otg_rev'. It defaults to HNP and SRP bmAttributes if unspecified. There may be a mismatch with what's being set in dwc2 params structure. This result in the descriptors to be miss-configured in this case. So replace 'otg_cap' bit field by 'otg_caps' structure, so hnp, srp and otg_rev' can be configured directly in the params. It's then provided to the gadget struct. These parameters can be tuned for each platform. In case it's not set, it will default to current behavior. Also add option to setup these from the device tree by calling of_usb_update_otg_caps(). This provides support for standard properties such as "otg-rev", "hnp-disable" and "srp-disable" (see usb-drd.yaml). Signed-off-by: Fabrice Gasnier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-07-21usb: dwc2: Skip clock gating on Samsung SoCsMarek Szyprowski1-0/+1
Commit 0112b7ce68ea ("usb: dwc2: Update dwc2_handle_usb_suspend_intr function.") changed the way the driver handles power down modes in a such way that it uses clock gating when no other power down mode is available. This however doesn't work well on the DWC2 implementation used on the Samsung SoCs. When a clock gating is enabled, system hangs. It looks that the proper clock gating requires some additional glue code in the shared USB2 PHY and/or Samsung glue code for the DWC2. To restore driver operation on the Samsung SoCs simply skip enabling clock gating mode until one finds what is really needed to make it working reliably. Fixes: 0112b7ce68ea ("usb: dwc2: Update dwc2_handle_usb_suspend_intr function.") Cc: stable <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Marek Szyprowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-05-27usb: dwc2: params: Fix naming of 'dwc2_get_hwparams()' in the docsLee Jones1-2/+2
Fixes the following W=1 kernel build warning(s): drivers/usb/dwc2/params.c:787: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst Cc: Minas Harutyunyan <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Lee Jones <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-04-22usb: dwc2: Enable RPi in ACPI modeJeremy Linton1-1/+17
The dwc2 driver has everything we need to run in ACPI mode except for the ACPI module device table boilerplate. With that added and identified as "BCM2848", an id in use by other OSs for this device, the dw2 controller on the BCM2711 will work. Signed-off-by: Jeremy Linton <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-01-12usb: dwc2: disable Link Power Management on STM32MP15 HS OTGAmelie Delaunay1-0/+4
Link Power Management (LPM) on STM32MP15 OTG HS encounters instabilities with some Host controllers. OTG core fails to exit L1 state in 200us: "dwc2 49000000.usb-otg: Failed to exit L1 sleep state in 200us." Then the device is still not enumerated. To avoid this issue, disable Link Power Management on STM32MP15 HS OTG. Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Amelie Delaunay <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-01-12usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTGAmelie Delaunay1-0/+2
When the core is in FS host mode, using the FS transceiver, and a Low-Speed device is connected, transceiver clock is 6Mhz. So, to support Low-Speed devices, enable support of FS/LS Low Power mode, so that the PHY supplies a 6 MHz clock during Low-Speed mode. Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Amelie Delaunay <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-01-12usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FSAmelie Delaunay1-0/+2
STM32MP15 ahbcfg register default value sets Burst length/type (HBSTLEN) to Single (32-bit accesses on AHB), which is not recommended, according to STM32MP157 Reference manual [1]. This patch sets Burst length/type (HBSTLEN) so that bus transactions target 16x32 bit accesses. This improves OTG controller performance. [1] https://www.st.com/resource/en/reference_manual/dm00327659.pdf, p.3149 Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Amelie Delaunay <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-10-02usb: dwc2: don't use ID/Vbus detection if usb-role-switch on STM32MP15 SoCsAmelie Delaunay1-1/+1
If usb-role-switch is present in the device tree, it means that ID and Vbus signals are not connected to the OTG controller but to an external component (GPIOs, Type-C controller). In this configuration, usb role switch is used to force valid sessions on STM32MP15 SoCs. Acked-by: Minas Harutyunyan <[email protected]> Acked-by: Martin Blumenstingl <[email protected]> Signed-off-by: Amelie Delaunay <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-10-02usb: dwc2: add support for APM82181 USB OTGChristian Lamparter1-0/+1
adds the specific compatible string for the DWC2 IP found in the APM82181 SoCs. The IP is setup correctly through the auto detection... With the exception of the AHB Burst Size. The default of GAHBCFG_HBSTLEN_INCR4 of the "snps,dwc2" can cause a system hang when the USB and SATA is used concurrently. Because the predecessor (PPC460EX (Canyonlands)) already had the same problem, this SoC can make use of the existing dwc2_set_amcc_params() function. Signed-off-by: Christian Lamparter <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-09-24usb: dwc2: Fix parameter type in function pointer prototypeNathan Chancellor1-1/+1
When booting up on a Raspberry Pi 4 with Control Flow Integrity checking enabled, the following warning/panic happens: [ 1.626435] CFI failure (target: dwc2_set_bcm_params+0x0/0x4): [ 1.632408] WARNING: CPU: 0 PID: 32 at kernel/cfi.c:30 __cfi_check_fail+0x54/0x5c [ 1.640021] Modules linked in: [ 1.643137] CPU: 0 PID: 32 Comm: kworker/0:1 Not tainted 5.8.0-rc6-next-20200724-00051-g89ba619726de #1 [ 1.652693] Hardware name: Raspberry Pi 4 Model B Rev 1.2 (DT) [ 1.658637] Workqueue: events deferred_probe_work_func [ 1.663870] pstate: 60000005 (nZCv daif -PAN -UAO BTYPE=--) [ 1.669542] pc : __cfi_check_fail+0x54/0x5c [ 1.673798] lr : __cfi_check_fail+0x54/0x5c [ 1.678050] sp : ffff8000102bbaa0 [ 1.681419] x29: ffff8000102bbaa0 x28: ffffab09e21c7000 [ 1.686829] x27: 0000000000000402 x26: ffff0000f6e7c228 [ 1.692238] x25: 00000000fb7cdb0d x24: 0000000000000005 [ 1.697647] x23: ffffab09e2515000 x22: ffffab09e069a000 [ 1.703055] x21: 4c550309df1cf4c1 x20: ffffab09e2433c60 [ 1.708462] x19: ffffab09e160dc50 x18: ffff0000f6e8cc78 [ 1.713870] x17: 0000000000000041 x16: ffffab09e0bce6f8 [ 1.719278] x15: ffffab09e1c819b7 x14: 0000000000000003 [ 1.724686] x13: 00000000ffffefff x12: 0000000000000000 [ 1.730094] x11: 0000000000000000 x10: 00000000ffffffff [ 1.735501] x9 : c932f7abfc4bc600 x8 : c932f7abfc4bc600 [ 1.740910] x7 : 077207610770075f x6 : ffff0000f6c38f00 [ 1.746317] x5 : 0000000000000000 x4 : 0000000000000000 [ 1.751723] x3 : 0000000000000000 x2 : 0000000000000000 [ 1.757129] x1 : ffff8000102bb7d8 x0 : 0000000000000032 [ 1.762539] Call trace: [ 1.765030] __cfi_check_fail+0x54/0x5c [ 1.768938] __cfi_check+0x5fa6c/0x66afc [ 1.772932] dwc2_init_params+0xd74/0xd78 [ 1.777012] dwc2_driver_probe+0x484/0x6ec [ 1.781180] platform_drv_probe+0xb4/0x100 [ 1.785350] really_probe+0x228/0x63c [ 1.789076] driver_probe_device+0x80/0xc0 [ 1.793247] __device_attach_driver+0x114/0x160 [ 1.797857] bus_for_each_drv+0xa8/0x128 [ 1.801851] __device_attach.llvm.14901095709067289134+0xc0/0x170 [ 1.808050] bus_probe_device+0x44/0x100 [ 1.812044] deferred_probe_work_func+0x78/0xb8 [ 1.816656] process_one_work+0x204/0x3c4 [ 1.820736] worker_thread+0x2f0/0x4c4 [ 1.824552] kthread+0x174/0x184 [ 1.827837] ret_from_fork+0x10/0x18 CFI validates that all indirect calls go to a function with the same exact function pointer prototype. In this case, dwc2_set_bcm_params is the target, which has a parameter of type 'struct dwc2_hsotg *', but it is being implicitly cast to have a parameter of type 'void *' because that is the set_params function pointer prototype. Make the function pointer protoype match the definitions so that there is no more violation. Fixes: 7de1debcd2de ("usb: dwc2: Remove platform static params") Link: https://github.com/ClangBuiltLinux/linux/issues/1107 Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-07-27Revert "usb: dwc2: don't use ID/Vbus detection if usb-role-switch on ↵Greg Kroah-Hartman1-3/+1
STM32MP15 SoCs" This reverts commit 916f8b627288039d9e771a9b2ab1b3c79b303039. This was not meant to be applied as-is at the moment. Cc: Minas Harutyunyan <[email protected]> Cc: Amelie Delaunay <[email protected]> Cc: Felipe Balbi <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-07-23usb: dwc2: don't use ID/Vbus detection if usb-role-switch on STM32MP15 SoCsAmelie Delaunay1-1/+3
If usb-role-switch is present in the device tree, it means that ID and Vbus signals are not connected to the OTG controller but to an external component (GPIOs, Type-C controller). In this configuration, usb role switch is used to force valid sessions on STM32MP15 SoCs. Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Amelie Delaunay <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-06-18usb: dwc2: use well defined macros for power_downJisheng Zhang1-6/+6
Use the well defined macros such as DWC2_POWER_DOWN_PARAM_NONE, DWC2_POWER_DOWN_PARAM_PARTIAL and DWC2_POWER_DOWN_PARAM_HIBERNATION to make code more readable. Signed-off-by: Jisheng Zhang <[email protected]> Acked-by: Minas Harutyunyan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-05-25usb: dwc2: Update Core Reset programming flow.Minas Harutyunyan1-19/+0
Starting from core version 4.20a Core Reset flow is changed. Introduced new bit in GRSTCTL register - GRSTCTL_CSFTRST_DONE. Core Reset new programming flow steps are follow: 1. Set GRSTCTL_CSFTRST bit. 2. Wait for bit GRSTCTL_CSFTRST_DONE is set. 3. Clear GRSTCTL_CSFTRST and GRSTCTL_CSFTRST_DONE bits. Check core version functionality separated from dwc2_get_hwparams() to new dwc2_check_core_version() function because Core Reset flow depend on SNPSID. Signed-off-by: Minas Harutyunyan <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2020-03-15usb: dwc2: add support for STM32MP15 SoCs USB OTG HS and FSAmelie Delaunay1-0/+33
This patch introduces a new parameter to activate external ID pin and valid vbus level detection, required on STM32MP15 SoC to support dual role, either in HS or FS. The STM32MP15 SoC uses the GGPIO register to enable the level detection. The level detector requires to be powered. Also adds the params structures for STM32MP15 OTG HS and STM32MP1 OTG FS. Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Amelie Delaunay <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-07-25usb: dwc2: Switch to use device_property_count_u32()Andy Shevchenko1-4/+1
Use use device_property_count_u32() directly, that makes code neater. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Minas Harutyunyan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-07-01Merge tag 'usb-for-v5.3' of ↵Greg Kroah-Hartman1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next Felipe writes: usb: changes for v5.3 merge window The biggest part here is a set of patches removing unnecesary variables from several drivers. Meson-g12a's dwc3 glue implemented IRQ-based OTG/DRD role swap. Qcom's dwc3 glue added support for ACPI, mainly for the AArch64-based SoCs. DWC3 also got support for Intel Elkhart Lake platforms. * tag 'usb-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb: (30 commits) usb: dwc3: remove unused @lock member of dwc3_ep struct usb: dwc3: pci: Add Support for Intel Elkhart Lake Devices usb: Replace snprintf with scnprintf in gether_get_ifname usb: gadget: ether: Fix race between gether_disconnect and rx_submit usb: gadget: storage: Remove warning message usb: dwc3: gadget: Add support for disabling U1 and U2 entries usb: gadget: send usb_gadget as an argument in get_config_params doc: dt: bindings: usb: dwc3: Update entries for disabling U1 and U2 usb: dwc3: qcom: Use of_clk_get_parent_count() usb: dwc3: Fix core validation in probe, move after clocks are enabled usb: dwc3: qcom: Improve error handling usb: dwc3: qcom: Start USB in 'host mode' on the SDM845 usb: dwc3: qcom: Add support for booting with ACPI soc: qcom: geni: Add support for ACPI Revert "usb: dwc2: host: Setting qtd to NULL after freeing it" usb: gadget: net2272: remove redundant assignments to pointer 's' usb: gadget: Zero ffs_io_data USB: omap_udc: Remove unneeded variable fotg210-udc: Remove unneeded variable usb: gadget: at91_udc: Remove unneeded variable ...
2019-06-18usb: dwc2: Force 8bit UTMI width for Samsung Exynos SoCsMarek Szyprowski1-0/+1
Samsung Exynos SoCs require to force UTMI width to 8bit, otherwise the host side of the shared USB2 PHY doesn't work. Reported-by: Krzysztof Kozlowski <[email protected]> Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width") Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Minas Harutyunyan <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Tested-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-06-18usb: dwc2: Use generic PHY width in params setupJules Maselbas1-0/+9
Setting params.phy_utmi_width in dwc2_lowlevel_hw_init() is pointless since it's value will be overwritten by dwc2_init_params(). This change make sure to take in account the generic PHY width information during paraminitialisation, done in dwc2_set_param_phy_utmi_width(). By doing so, the phy_utmi_width params can still be overrided by devicetree specific params and will also be checked against hardware capabilities. Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width") Acked-by: Minas Harutyunyan <[email protected]> Tested-by: Marek Szyprowski <[email protected]> Signed-off-by: Jules Maselbas <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-05-03usb: dwc2: Set lpm mode parameters depend on HW configurationMinas Harutyunyan1-5/+18
If core not supported lpm, i.e. BCM2835 then confusing warnings seen in log. To avoid these warnings, added function dwc2_set_param_lpm() to set lpm and other lpm related parameters based on lpm support by core. Signed-off-by: Minas Harutyunyan <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2019-05-03usb: dwc2: Add Amlogic G12A DWC2 ParamsNeil Armstrong1-0/+12
This patchs sets the params for the DWC2 Controller found in the Amlogic G12A SoC family. It mainly sets the settings reported incorrect by the driver, leaving the remaining detected automatically by the driver and provided by the DT node. Signed-off-by: Neil Armstrong <[email protected]> Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-12-10usb: dwc2: disable power_down on Amlogic devicesMartin Blumenstingl1-0/+1
Disable power_down by setting the parameter to DWC2_POWER_DOWN_PARAM_NONE. This fixes a problem on various Amlogic Meson SoCs where USB devices are only recognized when plugged in before booting Linux. A hot-plugged USB device was not detected even though the device got power (my USB thumb drive for example has an LED which lit up). A similar fix was implemented for Rockchip SoCs in commit c216765d3a1def ("usb: dwc2: disable power_down on rockchip devices"). That commit suggests that a change in the dwc2 driver is the cause because the default value for the "hibernate" parameter (which then got renamed to "power_down" to support other modes) was changed in the v4.17 merge window with: commit 6d23ee9caa6790 ("Merge tag 'usb-for-v4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-testing"). Cc: <[email protected]> # 4.19 Acked-by: Minas Harutyunyan <[email protected]> Suggested-by: Christian Hewitt <[email protected]> Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-12-05usb: dwc2: Disable power down feature on Samsung SoCsMarek Szyprowski1-1/+9
Power down feature of DWC2 module integrated in Samsung SoCs doesn't work properly or needs some additional handling in PHY or SoC glue layer, so disable it for now. Without disabling power down, DWC2 causes random memory trashes and fails enumeration if there is no USB link to host on driver probe. Fixes: 03ea6d6e9e1ff1 ("usb: dwc2: Enable power down") Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-10-05usb: dwc2: disable power_down on rockchip devicesSolidHal1-0/+1
The bug would let the usb controller enter partial power down, which was formally known as hibernate, upon boot if nothing was plugged in to the port. Partial power down couldn't be exited properly, so any usb devices plugged in after boot would not be usable. Before the name change, params.hibernation was false by default, so _dwc2_hcd_suspend() would skip entering hibernation. With the rename, _dwc2_hcd_suspend() was changed to use params.power_down to decide whether or not to enter partial power down. Since params.power_down is non-zero by default, it needs to be set to 0 for rockchip devices to restore functionality. This bug was reported in the linux-usb thread: REGRESSION: usb: dwc2: USB device not seen after boot The commit that caused this regression is: 6d23ee9caa6790aea047f9aca7f3c03cb8d96eb6 Signed-off-by: SolidHal <[email protected]> Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-10-02usb: dwc2: gadget: Add parameters for GREFCLK registerGrigor Tovmasyan1-0/+2
Added ref_clk_per and sof_cnt_wkup_alert parameters in dwc2_core_params struct and set default values. Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Grigor Tovmasyan <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-10-02usb: dwc2: Add core parameter for service interval supportGrigor Tovmasyan1-0/+4
Added core parameter for service interval based scheduling. Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Grigor Tovmasyan <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-07-30usb: dwc2: Turn on uframe_sched on "stm32f4x9_fsotg" platformsDouglas Anderson1-1/+0
There's no reason to have the uframe scheduler off on dwc2. Running with uframe_sched = False is equivalent to saying "I don't want to run the correct code, I want to run the old and incorrect code". The uframe scheduler has been off on stm32f4x9_fsotg since commit e35b135055e2 ("usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)"). That commit is pretty recent, so it's unclear to me why the uframe scheduler was left off. Hopefully it's because someone copied it from other parameters and didn't think to try it? Presumably if everyone is good w/ the uframe_sched turned back on we can kill all the old and crufty non-uframe sched code. Reviewed-by: Minas Harutyunyan <[email protected]> Signed-off-by: Douglas Anderson <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-07-30usb: dwc2: Turn on uframe_sched on "amlogic" platformsDouglas Anderson1-1/+0
There's no reason to have the uframe scheduler off on dwc2. Running with uframe_sched = False is equivalent to saying "I don't want to run the correct code, I want to run the old and incorrect code". The uframe scheduler has been off on Amlogic since commit f94310ac076e ("usb: dwc2: add support for Meson8b and GXBB SoCs"). While this was after most of the recent improvements, notably the commit 9f9f09b048f5 ("usb: dwc2: host: Totally redo the microframe scheduler"), presumably the parameters were copied from another platform and the uframe scheduler wasn't tried. Presumably if everyone is good w/ the uframe_sched turned back on we can kill all the old and crufty non-uframe sched code. Reviewed-by: Minas Harutyunyan <[email protected]> Signed-off-by: Douglas Anderson <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-07-30usb: dwc2: Turn on uframe_sched on "his" platformsDouglas Anderson1-1/+0
There's no reason to have the uframe scheduler off on dwc2. Running with uframe_sched = False is equivalent to saying "I don't want to run the correct code, I want to run the old and incorrect code". The uframe scheduler has been off on HiSilicon since commit 37dd9d65cc41 ("usb: dwc2: add support of hi6220"). Since then there have been many many improvements, notably the commit 9f9f09b048f5 ("usb: dwc2: host: Totally redo the microframe scheduler") Presumably if everyone is good w/ the uframe_sched turned back on we can kill all the old and crufty non-uframe sched code. Acked-by: Minas Harutyunyan <[email protected]> Reviewed-by: Minas Harutyunyan <[email protected]> Signed-off-by: Douglas Anderson <[email protected]> Tested-by: John Stultz <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-07-30usb: dwc2: Turn on uframe_sched on "bcm" platformsDouglas Anderson1-1/+0
There's no reason to have the uframe scheduler off on dwc2. Running with uframe_sched = False is equivalent to saying "I don't want to run the correct code, I want to run the old and incorrect code". The uframe scheduler has been off on Broadcom since commit 58b179dcf28c ("staging: dwc2: disable uframe_sched on the bcm2835"). Since then there have been many many improvements, notably the commit 9f9f09b048f5 ("usb: dwc2: host: Totally redo the microframe scheduler") Presumably if everyone is good w/ the uframe_sched turned back on we can kill all the old and crufty non-uframe sched code. Reviewed-by: Minas Harutyunyan <[email protected]> Signed-off-by: Douglas Anderson <[email protected]> Tested-by: Stefan Wahren <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-07-30usb: dwc2: Modify dwc2_readl/writel functions prototypeGevorg Sahakyan1-10/+10
Added hsotg argument to dwc2_readl/writel function prototype, and also instead of address pass offset of register. hsotg will contain flag field for endianness. Also customized dwc2_set_bit and dwc2_clear_bit function for dwc2_readl/writel functions. Signed-off-by: Gevorg Sahakyan <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-05-21usb: dwc2: gadget: Fix coverity issueGrigor Tovmasyan1-1/+1
When _param is unsigned and the minimum value of range is 0, it gives the following warning: COVERITY NO_EFFECT: This less-than-zero comparison of an unsigned value is never true. Converting ._param to int to avoid this warning. Signed-off-by: Grigor Tovmasyan <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-05-21usb: dwc2: Fix HiKey regression caused by power_down featureJohn Stultz1-0/+1
In 4.17-rc, commit 03ea6d6e9e1f ("usb: dwc2: Enable power down") caused the HiKey board to not correctly handle switching between usb-gadget and usb-host mode. Unplugging the OTG port would result in: [ 42.240973] dwc2 f72c0000.usb: dwc2_restore_host_registers: no host registers to restore [ 42.249066] dwc2 f72c0000.usb: dwc2_host_exit_hibernation: failed to restore host registers And the USB-host ports would not function. And plugging in the OTG port, we would see: [ 46.046557] WARNING: CPU: 3 PID: 6 at drivers/usb/dwc2/gadget.c:260 dwc2_hsotg_init_fifo+0x194/0x1a0 [ 46.055761] CPU: 3 PID: 6 Comm: kworker/u16:0 Not tainted 4.17.0-rc5-00030-ge67da8c #231 [ 46.055767] Hardware name: HiKey Development Board (DT) [ 46.055784] Workqueue: dwc2 dwc2_conn_id_status_change ... Thus, this patch sets the hisi params to disable the power_down flag by default, and gets thing working again. Cc: John Youn <[email protected]> Cc: Vardan Mikayelyan <[email protected]> Cc: Artur Petrosyan <[email protected]> Cc: Grigor Tovmasyan <[email protected]> Cc: Felipe Balbi <[email protected]> Cc: [email protected] Signed-off-by: John Stultz <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
2018-05-21usb: dwc2: Fix kernel doc's warnings.Grigor Tovmasyan1-0/+8
Added descriptions for all not described parameters. Fix all kernel doc's warnings. Acked-by: Minas Harutyunyan <[email protected]> Signed-off-by: Grigor Tovmasyan <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.