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path: root/drivers/soc/sifive
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2023-11-22soc: sifive: shunt ccache driver to drivers/cacheConor Dooley3-285/+0
Move the ccache driver over to drivers/cache, out of the drivers/soc dumping ground, to this new collection point for cache controller drivers. Reviewed-by: Samuel Holland <[email protected]> Tested-by: Samuel Holland <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-09-18soc: sifive: replace SOC_FOO with ARCH_FOOConor Dooley1-1/+1
As part of unifiying what RISC-V calls microarch symbols to use ARCH_, replace users of the SOC_ forms. Signed-off-by: Conor Dooley <[email protected]>
2022-12-26soc: sifive: ccache: Add StarFive JH7110 supportEmil Renner Berthing1-1/+1
This adds support for the StarFive JH7110 SoC which also features this SiFive cache controller. Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Hal Feng <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2022-11-09soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()Yang Yingliang1-4/+11
The device_node pointer returned by of_find_matching_node() with refcount incremented, when finish using it, the refcount need be decreased. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2022-11-09soc: sifive: ccache: fix missing free_irq() in error path in ↵Yang Yingliang1-1/+4
sifive_ccache_init() Add missing free_irq() before return error from sifive_ccache_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2022-11-09soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()Yang Yingliang1-4/+11
Add missing iounmap() before return error from sifive_ccache_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2022-10-13soc: sifive: ccache: define the macro for the register shiftsZong Li1-5/+11
Define the macro for the register shifts, it could make the code be more readable Signed-off-by: Zong Li <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2022-10-13soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixesBen Dooks1-7/+10
Use the pr_fmt() macro to prefix all the output with "CCACHE:" to avoid having to write it out each time, or make a large diff when the next change comes along. Signed-off-by: Ben Dooks <[email protected]> Signed-off-by: Zong Li <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2022-10-13soc: sifive: ccache: reduce printing on initBen Dooks1-14/+11
The driver prints out 6 lines on startup, which can easily be redcued to two lines without losing any information. Note, to make the types work better, uint64_t has been replaced with ULL to make the unsigned long long match the format in the print statement. Signed-off-by: Ben Dooks <[email protected]> Signed-off-by: Zong Li <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2022-10-13soc: sifive: ccache: determine the cache level from dtsZong Li1-1/+5
Composable cache could be L2 or L3 cache, use 'cache-level' property of device node to determine the level. Signed-off-by: Zong Li <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2022-10-13soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.Greentime Hu4-241/+249
Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <[email protected]> Signed-off-by: Zong Li <[email protected]> Co-developed-by: Zong Li <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
2021-01-07RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740Yash Shah1-3/+24
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540. Update the L2 cache controller driver to support this additional interrupt in case of FU740-C000 chip. Signed-off-by: Yash Shah <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]>
2020-05-28soc: sifive: l2 cache: Mark l2_get_priv_group as staticPalmer Dabbelt1-1/+1
The kbuild test robot is firing a warning over a missing prototype. The function can just be static. Reported-by: kbuild test robot <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]>
2020-05-28soc: sifive: l2 cache: Eliminate an unsigned zero compare warningPalmer Dabbelt1-1/+1
GCC warns about this comparison, which is unnecessary. Signed-off-by: Palmer Dabbelt <[email protected]>
2020-05-20riscv: Add support to determine no. of L2 cache way enabledYash Shah1-0/+38
In order to determine the number of L2 cache ways enabled at runtime, implement a private attribute ("number_of_ways_enabled"). Reading this attribute returns the number of enabled L2 cache ways at runtime. Using riscv_set_cacheinfo_ops() hook a custom function, that returns this private attribute, to the generic ops structure which is used by cache_get_priv_group() in cacheinfo framework. Signed-off-by: Yash Shah <[email protected]> Reviewed-by: Anup Patel <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]>
2020-01-12riscv: move sifive_l2_cache.h to include/socYash Shah1-1/+1
The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") moves the sifive L2 cache driver to driver/soc. It did not move the header file along with the driver. Therefore this patch moves the header file to driver/soc Signed-off-by: Yash Shah <[email protected]> Reviewed-by: Anup Patel <[email protected]> [[email protected]: updated to fix the include guard] Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") Signed-off-by: Paul Walmsley <[email protected]>
2019-12-20riscv: move sifive_l2_cache.c to drivers/socChristoph Hellwig3-0/+191
The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs. Move the file to drivers/soc and add a Kconfig option for it, as well as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig <[email protected]> Reviewed-by: Borislav Petkov <[email protected]> [[email protected]: keep the MAINTAINERS change specific to the L2$ controller code] Signed-off-by: Paul Walmsley <[email protected]>
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