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path: root/drivers/pinctrl/sunxi/Kconfig
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2022-07-18pinctrl: sunxi: Add driver for Allwinner D1Samuel Holland1-0/+5
This SoC contains a pinctrl with a new register layout. Use the variant parameter to set the right register offsets. This pinctrl also increases the number of functions per pin from 8 to 16, taking advantage of all 4 bits in the mux config field (so far, only functions 0-8 and 14-15 are used). This increases the maximum possible number of functions. Reviewed-by: Heiko Stuebner <[email protected]> Tested-by: Heiko Stuebner <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-06-15pinctrl: sunxi: Remove reset controller consumersSamuel Holland1-3/+0
None of the sunxi pin controllers have a module reset line. All of the SoC documentation, where available, agrees. The bits that would be used for the PIO reset (i.e. matching the order of the clock gate bits) are always reserved, both in the CCU and in the PRCM. And experiments on several SoCs, including the A33, confirm that those reserved bits indeed have no effect. Let's remove this superfluous code and dependency, and also remove the include statement that was copied to the other r_pio drivers. Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-21pinctrl: sunxi: Add support for the Allwinner H616-R pin controllerAndre Przywara1-0/+5
There are only two pins left now, used to connect to the PMIC via I2C. Signed-off-by: Andre Przywara <[email protected]> Acked-by: Maxime Ripard <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-01-21pinctrl: sunxi: Add support for the Allwinner H616 pin controllerAndre Przywara1-0/+5
Port A is used for an internal connection to some analogue circuitry which looks like an AC200 IP (as in the H6), though this is not mentioned in the manual. Signed-off-by: Andre Przywara <[email protected]> Acked-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2020-09-12pinctrl: sunxi: add support for the Allwinner A100 pin controllerYangtao Li1-0/+10
This commit introduces support for the pin controller on A100. Signed-off-by: Yangtao Li <[email protected]> Acked-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/4e331a2ed4a30c883df6157bc5c52bb686aa8e0d.1595572867.git.frank@allwinnertech.com Signed-off-by: Linus Walleij <[email protected]>
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-04-04pinctrl: sunxi: Allow to disable pinctrl driversMaxime Ripard1-19/+38
Our pinctrl drivers are consisting of some common code, and big pin tables that are SoC-specific. This is fine in most cases, but when you want to reduce the size of the particular kernel image, those big tables are, well, quite big. We haven't had the option to disable them in the past since they were hidden Kconfig options based on the SoC support. However, that granularity isn't great since we don't have one Kconfig option per-SoC, but rather one by family. Make those options selectable by the user so that they can disable it if needed, while keeping the current default to not change the standard case. Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-11-25pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)Mesih Kilinc1-0/+4
The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a pin controller like other SoCs from Allwinner. Add support for it. Signed-off-by: Mesih Kilinc <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-05-16pinctrl: sunxi: add support for H6 R_PIO pin controllerIcenowy Zheng1-0/+4
Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs, which controls the PL and PM pin banks. Add support for it. Signed-off-by: Icenowy Zheng <[email protected]> Acked-by: Maxime Ripard <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2018-03-27pinctrl: sunxi: add support for the Allwinner H6 main pin controllerIcenowy Zheng1-0/+4
The Allwinner H6 SoC has two pin controllers, one main controller (called CPUX-PORT in user manual) and one controller in CPUs power domain (called CPUS-PORT in user manual). This commit introduces support for the main pin controller on H6. The pin bank A and B are not wired out and hidden from the SoC's documents, however it's shown that the "ATE" (an AC200 chip co-packaged with the H6 die) is connected to the main SoC die via these pin banks. The information about these banks is just copied from the BSP pinctrl driver, but re-formatted to fit the mainline pinctrl driver format. The GPIO functions are dropped, as they're impossible to use -- except a GPIO&IRQ only pin (PB20) which might be the IRQ of ATE. Signed-off-by: Icenowy Zheng <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2017-08-14pinctrl: sunxi: add support of R40 to A10 pinctrl driverIcenowy Zheng1-1/+1
R40 is said to be an upgrade of A20, and its pin configuration is also similar to A20 (and thus similar to A10). Add support for R40 to the A10 pinctrl driver. Signed-off-by: Icenowy Zheng <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2017-06-09pinctrl: sunxi: Add support for A83T R_PIOChen-Yu Tsai1-0/+4
The R_PIO on the A83T is almost the same as the one found on the A64, except that the CIR_RX function was moved from pin PL11 to pin PL12. Add a driver for it. Signed-off-by: Chen-Yu Tsai <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2017-05-29pinctrl: sunxi: drop dedicated A20 driverIcenowy Zheng1-4/+0
As we added A20 support to A10 pinctrl driver, now we can delete the dedicated A20 pinctrl driver, which is duplicated code. Signed-off-by: Icenowy Zheng <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> [Drop Makefile entry] Signed-off-by: Linus Walleij <[email protected]>
2017-05-29pinctrl: sunxi: add A20 support to A10 driverIcenowy Zheng1-2/+2
As A20 is designed as a pin-compatible upgrade of A10, their pin controller are very similar, and can share one driver. Add A20 support to the A10 driver. Signed-off-by: Icenowy Zheng <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2017-03-14pinctrl: sunxi: select GPIOLIBIcenowy Zheng1-0/+1
Allwinner pin controllers are also GPIO controllers. Currently, if GPIOLIB is forgot to be chosen, the build of pinctrl-sunxi.c will fail for lacking a lot of gpiochip_* functions. Select GPIOLIB to ensure this driver can be built. Signed-off-by: Icenowy Zheng <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2017-03-14pinctrl: sunxi: Add A64 R_PIO controller supportIcenowy Zheng1-0/+4
The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC. Add support for the pins controlled by the R_PIO controller. Signed-off-by: Icenowy Zheng <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2017-03-14pinctrl: sunxi: refactor pinctrl choice selecting for ARM64Icenowy Zheng1-4/+4
ARM64 Allwinner SoCs used to have every pinctrl driver selected in ARCH_SUNXI. Change this to make their default value to (ARM64 && ARCH_SUNXI). Signed-off-by: Icenowy Zheng <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2017-02-06pinctrl: sunxi: Remove redundant A31s pinctrl driverChen-Yu Tsai1-4/+0
Now that we can support the A31s pin controller with the A31 driver using the new variants support, the independent A31s driver becomes redundant. Remove it. Signed-off-by: Chen-Yu Tsai <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2017-01-30drivers: pinctrl: add driver for Allwinner H5 SoCIcenowy Zheng1-0/+4
Based on the Allwinner H5 datasheet and the pinctrl driver of the backward-compatible H3 this introduces the pin multiplex assignments for the H5 SoC. H5 introduced some more pin functions (e.g. three more groups of TS pins, and one more groups of SIM pins) than H3. Signed-off-by: Icenowy Zheng <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2017-01-11pinctrl: sunxi: add driver for V3s SoCIcenowy Zheng1-0/+4
V3s SoC features only a pin controller (for the lack of CPUs part). Add a driver for this controller. Signed-off-by: Icenowy Zheng <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2017-01-09pinctrl: sunxi: Remove old sun5i pinctrl driversMaxime Ripard1-11/+0
Now that we have a common pinctrl driver for all the sun5i SoCs, we can remove the old, separate drivers. Signed-off-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2017-01-09pinctrl: sunxi: Add common sun5i pinctrl driverMaxime Ripard1-0/+3
The sun5i SoCs (A10s, A13, GR8) are all based on the same die fit in different packages. Hence, the pins and functions available are just the based on the same set, each SoC having a different subset. Introduce a common pinctrl driver that supports multiple variants to allow to put as much as we can in common. Signed-off-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-09-07pinctrl: sunxi: Add GR8 controller supportMylène Josserand1-0/+4
Just like the other member of the sunxi family, let's add a pinctrl table for the muxing options. Signed-off-by: Mylène Josserand <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-03-11drivers: pinctrl: add driver for Allwinner A64 SoCAndre Przywara1-0/+4
Based on the Allwinner A64 user manual and on the previous sunxi pinctrl drivers this introduces the pin multiplex assignments for the ARMv8 Allwinner A64 SoC. Port A is apparently used for the fixed function DRAM controller, so the ports start at B here (the manual mentions "n from 1 to 7", so not starting at 0). Signed-off-by: Andre Przywara <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-02-11pinctrl: sunxi: Add H3 R_PIO controller supportKrzysztof Adamski1-0/+4
H3 has additional PIO controller similar to what we can find on A23. It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350. Signed-off-by: Krzysztof Adamski <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2016-01-28pinctrl: sunxi: guard sub-directory with CONFIG_PINCTRL_SUNXIMasahiro Yamada1-15/+15
CONFIG_PINCTRL_SUNXI is more suitable than CONFIG_ARCH_SUNXI to guard the drivers/pinctrl/sunxi/ directory. (I renamed CONFIG_PINCTRL_SUNXI_COMMON to CONFIG_PINCTRL_SUNXI.) Signed-off-by: Masahiro Yamada <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2015-12-22pinctrl: sunxi: Add A80 special pin controllerMaxime Ripard1-0/+5
Like the previous designs, the A80 has a special pin controller for the critical pins, like the PMIC bus. Add a driver for this controller. Signed-off-by: Maxime Ripard <[email protected]> [wens: Add A80 compatible strings to bindings doc; fix pin function names based on v1.3 datasheet; constify of_device_id table] Signed-off-by: Chen-Yu Tsai <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2015-12-11pinctrl: sunxi: Add H3 PIO controller supportJens Kuske1-0/+4
The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2015-10-02pinctrl: sunxi: add allwinner A83T PIO controller supportVishnu Patekar1-0/+4
Allwinner A83T soc port controller has 8 ports. It has 3 IRQ banks namely PB, PG, PH. Pinmuxing are different for some pins as compared to sun8i A23 and A33. Signed-off-by: Vishnu Patekar <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2015-06-04pinctrl: sunxi: Add allwinner A33 PIO controller supportVishnu Patekar1-0/+4
A33 PIO has 7 ports which starts from PB and has two interrupt ports. Signed-off-by: Vishnu Patekar <[email protected]> Acked-by: Hans de Goede <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2015-01-14pinctrl: sun6i: Add A31s pinctrl supportHans de Goede1-0/+4
The A31s is a stripped down version of the A31, as such it is missing some pins and some functions on some pins. The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c with the missing pins and functions removed. Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the prcm pins are identical between the A31 and the A31s. Signed-off-by: Hans de Goede <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-10-30pinctrl: sunxi: Add A80 pinctrl muxing optionsMaxime Ripard1-0/+4
The A80 has a rather usual pin controller, the only thing out of the ordinary being that it has 5 interrupts banks, and that some pins have several options for the same functions. Signed-off-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-07-11pinctrl: sunxi: Add A23 R_PIO controller supportChen-Yu Tsai1-0/+5
The A23 has a R_PIO pin controller, similar to the one found on the A31 SoC. Add support for the pins controlled by the R_PIO controller. Signed-off-by: Chen-Yu Tsai <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-07-11pinctrl: sunxi: Add A23 PIO controller supportChen-Yu Tsai1-0/+4
The A23 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Chen-Yu Tsai <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-07-11pinctrl: sunxi: Remove PINCTRL_SUNXIMaxime Ripard1-9/+6
The PINCTRL_SUNXI configuration was kept only to deal with the introduction of per-machine symbols and the various pintrl drivers through different tree. Now that it's not useful anymore, we can just remove it. Signed-off-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-27pinctrl: sunxi: depend on RESET_CONTROLLERMaxime Ripard1-0/+1
The A31 R_PIO driver depends on the reset framework in a mandatory way. Express this by adding a depends on the reset framework in Kconfig Signed-off-by: Maxime Ripard <[email protected]> Reported-by: Arnd Bergmann <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: sunxi: Fix recursive dependencyMaxime Ripard1-12/+15
Fix the following configuration error: drivers/pinctrl/sunxi/Kconfig:3:error: recursive dependency detected! drivers/pinctrl/sunxi/Kconfig:3: symbol PINCTRL_SUNXI is selected by PINCTRL_SUN4I_A10 drivers/pinctrl/sunxi/Kconfig:9: symbol PINCTRL_SUN4I_A10 default value contains PINCTRL_SUNXI Add a new intermedia PINCTRL_SUNXI_COMMON, that superseeds the PINCTRL_SUNXI one. We still need to keep PINCTRL_SUNXI at the moment in order to preserve bisectability. Indeed, during that merge window, we also introduced the MACH_SUN* symbols. Since it's going through different trees, we can't rely on the fact that the options will be there, while ARCH_SUNXI still select PINCTRL_SUNXI. Signed-off-by: Maxime Ripard <[email protected]> Suggested-by: Arnd Bergmann <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: sunxi: Enable the pinctrl Kconfig options by defaultMaxime Ripard1-6/+6
Enable the freshly introduced Kconfig options whenever their matching architecture is enabled. Since the Kconfig symbols for these machines are going through a different tree, keep PINCTRL_SUNXI around for the moment to avoid breaking the defconfig. It should be removed eventually. Signed-off-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-04pinctrl: sunxi: Introduce per-driver Kconfig optionsMaxime Ripard1-0/+24
Add one Kconfig option for each driver. This will allow to better control which driver is enabled, instead of having either all or nothing. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-03pinctrl: sunxi: Move the Allwinner pinctrl driver to its own directoryMaxime Ripard1-0/+8
This will allow to create numerous files without crippling the main pinctrl directory. Signed-off-by: Maxime Ripard <[email protected]>
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