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2024-06-26pinctrl: qcom: Introduce SM4250 LPI pinctrl driverSrinivas Kandagatla1-0/+9
Add support for the pin controller block on SM4250 Low Power Island. Signed-off-by: Srinivas Kandagatla <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-02-21pinctrl: qcom: sm8650-lpass-lpi: correct Kconfig nameKrzysztof Kozlowski1-1/+1
Use proper model name in SM8650 LPASS pin controller Kconfig entry. Cc: <[email protected]> Fixes: c4e47673853f ("pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASS") Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-11-13pinctrl: qcom: sm8650-lpass-lpi: add SM8650 LPASSKrzysztof Kozlowski1-0/+10
Add driver for the pin controller in Low Power Audio SubSystem (LPASS) of Qualcomm SM8650 SoC. Notable differences against SM8550 LPASS pin controller: 1. Additional address space for slew rate thus driver uses LPI_FLAG_SLEW_RATE_SAME_REG and sets slew rate via different register. 2. Two new pin mux functions: qca_swr_clk and qca_swr_data Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-07-26pinctrl: qcom: Introduce SM6115 LPI pinctrl driverKonrad Dybcio1-0/+9
Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2023-07-24pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMMKrzysztof Kozlowski1-0/+10
Add driver for pin controller in Low Power Audio SubSystem (LPASS). The driver is similar to SM8250 LPASS pin controller, with difference in one new pin (gpio14) belonging to swr_tx_data. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2023-06-09pinctrl: qcom: organize audio drivers in menuconfigKrzysztof Kozlowski1-12/+12
The audio pin controller drivers depend on PINCTRL_LPASS_LPI, but since PINCTRL_LPASS_LPI is not the first entry, they are not displayed in menuconfig as dependent of PINCTRL_LPASS_LPI. Re-order the entries to fix this. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-06-09pinctrl: qcom: organize main SoC drivers in new Kconfig.msmKrzysztof Kozlowski1-412/+1
In menuconfig, some entries depending on PINCTRL_MSM are indented and expressed as dependening but some not, because of other Kconfig entries in between, Move all main Qualcomm SoC pin controller driver entries into new Kconfig.msm file so they will be nicely ordered in Kconfig file (by CONFIG_ name) and properly indented as PINCTRL_MSM dependency in menuconfig. Functionally this is the same, but since entire file is guarded with "if PINCTRL_MSM" drop this dependency from individual entries. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-06-09pinctrl: qcom: mark true OF dependency - common MSM pinctrl codeKrzysztof Kozlowski1-41/+2
The common MSM pinctrl driver code (PINCTRL_MSM) uses pinconf_generic_dt_node_to_map_group() from GENERIC_PINCONF, which is not available for compile testing for !OF cases. Drivers actually do not depend on OF. Move the OF dependency to the entry actually depending on it and drop any "|| COMPILE_TEST", because OF is required also for compile testing (lack of OF was never visible in compile testing because none of the drivers could be compile tested due to Makefile). Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-06-09pinctrl: qcom: drop unneeded GPIOLIB dependencyKrzysztof Kozlowski1-14/+8
PINCTRL_MSM depends on GPIOLIB, thus individual driver entries depending on the first do not have to depend on the latter. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-06-09pinctrl: qcom: correct language typo (Technologies)Krzysztof Kozlowski1-1/+1
Correct typo: Tehcnologies->Technologies. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-06-09pinctrl: qcom: fix indentation in KconfigKrzysztof Kozlowski1-2/+2
Use tab for correct Kconfig indentation. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-06-09pinctrl: qcom: Add IPQ5018 pinctrl driverSricharan Ramabadhran1-0/+11
Add pinctrl definitions for the TLMM of IPQ5018. Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Co-developed-by: Nitheesh Sekar <[email protected]> Signed-off-by: Nitheesh Sekar <[email protected]> Co-developed-by: Varadarajan Narayanan <[email protected]> Signed-off-by: Varadarajan Narayanan <[email protected]> Signed-off-by: Sricharan Ramabadhran <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-05-29pinctrl: qcom: Add SDX75 pincontrol driverRohit Agarwal1-10/+20
Add initial Qualcomm SDX75 pinctrl driver to support pin configuration with pinctrl framework for SDX75 SoC. While at it, reordering the SDX65 entry. Signed-off-by: Rohit Agarwal <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-03-19pinctrl: qcom: Add IPQ9574 pinctrl driverDevi Priya1-0/+11
Add pinctrl definitions for the TLMM of IPQ9574 Reviewed-by: Krzysztof Kozlowski <[email protected]> Co-developed-by: Anusha Rao <[email protected]> Signed-off-by: Anusha Rao <[email protected]> Signed-off-by: Devi Priya <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-03-19pinctrl: qcom: Add SM7150 pinctrl driverDanila Tikhonov1-0/+10
Add pinctrl driver for TLMM block found in SM7150 SoC. Signed-off-by: Danila Tikhonov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-02-07pinctrl: qcom: Introduce IPQ5332 TLMM driverKathiravan T1-0/+10
The IPQ5332 SoC comes with a TLMM block, like all other Qualcomm platforms, so add a driver for it. Signed-off-by: Kathiravan T <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-02-06pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASSKrzysztof Kozlowski1-0/+11
Add druver for pin controller in Low Power Audio SubSystem (LPASS). The driver is similar to SM8450 LPASS pin controller, with differences in few pin groups (qua_mi2s -> i2s0). Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-02-01pinctrl: qcom: add the tlmm driver sa8775p platformsYadu MG1-0/+9
Add support for Lemans TLMM configuration and control via the pinctrl framework. Signed-off-by: Yadu MG <[email protected]> Signed-off-by: Prasad Sodagudi <[email protected]> [Bartosz: made the driver ready for upstream] Co-developed-by: Bartosz Golaszewski <[email protected]> Signed-off-by: Bartosz Golaszewski <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2023-01-09pinctrl: qcom: Add SM8550 pinctrl driverAbel Vesa1-0/+10
Add pinctrl driver for TLMM block found in SM8550 SoC. Co-developed-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2022-12-29pinctrl: qcom: Add QDU1000/QRU1000 pinctrl driverMelody Olvera1-0/+10
Add pin control driver for the TLMM block found in the QDU1000 and QRU1000 SoC. Signed-off-by: Melody Olvera <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-10-17pinctrl: qcom: add sdm670 pinctrlRichard Acayan1-0/+10
The Snapdragon 670 has a Top-Level Mode Multiplexer (TLMM) for various features. Add a driver to support it. Link: https://android.googlesource.com/kernel/msm/+/de5a12173c7fa6d65bedee9ad36af55b2dbfeb36%5E%21/#F6 Link: https://android.googlesource.com/kernel/msm/+/04f083156d9b9f3bfcf204c1c6da88632fbb3863%5E%21/#F22 Link: https://android.googlesource.com/kernel/msm/+/54837652e3400ecc63ccc78b2193faf4f349a32e%5E%21/#F0 Link: https://android.googlesource.com/kernel/msm/+/f0409b07174ceca217f8b7fd255418feff06092d%5E%21/#F0 Signed-off-by: Richard Acayan <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-10-04pinctrl: qcom: restrict drivers per ARM/ARM64Krzysztof Kozlowski1-0/+39
There is no point to allow selecting pin-controller drivers for Qualcomm ARMv7 SoCs when building ARM64 kernel, and vice versa. This makes kernel configuration more difficult as many do not remember the Qualcomm SoCs. There won't be a single image for ARMv7 and ARMv8/9 SoCs, so no features/options are lost. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-25pinctrl: qcom: Add sc8280xp lpass lpi pinctrl driverSrinivas Kandagatla1-0/+9
Add pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SC8280XP. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[189 - 207] --> LPASS LPI GPIO [0 - 18] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-25pinctrl: qcom: Add sm8450 lpass lpi pinctrl driverSrinivas Kandagatla1-0/+9
Add pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8450. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[165 - 187] --> LPASS LPI GPIO [0 - 22] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-08-03pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSMJohn Garry1-1/+1
All the many other configs depend on config PINCTRL_MSM, yet for config PINCTRL_SM8450 we select config PINCTRL_MSM. Make config PINCTRL_SM8450 depend on PINCTRL_MSM to be consistent with the rest. Signed-off-by: John Garry <[email protected]> Suggested-by: Arnd Bergmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-26pinctrl: qcom: Add SM6375 TLMM driverKonrad Dybcio1-0/+9
Add a driver to control the TLMM block on SM6375. This is an adapted version of msm-5.4's pinctrl-blair driver. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-11pinctrl: qcom: Add pinctrl driver for MSM8909Stephan Gerhold1-0/+8
Make it possible to control pins using the TLMM block in the MSM8909 SoC by adding the necessary definitions for GPIOs, groups and functions. The driver is originally taken from the msm-4.9 release [1] from Qualcomm, but cleaned up significantly with several fixes and clarifications. [1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.7-22500-8x09.0/drivers/pinctrl/qcom/pinctrl-msm8909.c Signed-off-by: Stephan Gerhold <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-04-23pinctrl: qcom: Add SC7280 lpass pin configurationSrinivasa Rao Mandadapu1-0/+9
Add pin control support for SC7280 LPASS LPI. Signed-off-by: Srinivasa Rao Mandadapu <[email protected]> Co-developed-by: Venkata Prasad Potturu <[email protected]> Signed-off-by: Venkata Prasad Potturu <[email protected]> Reviewed-by: Matthias Kaehlcke <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-04-23pinctrl: qcom: Extract chip specific LPASS LPI codeSrinivasa Rao Mandadapu1-0/+9
Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver to allow reusing the common code in the addition of subsequent platforms. Signed-off-by: Srinivasa Rao Mandadapu <[email protected]> Co-developed-by: Venkata Prasad Potturu <[email protected]> Signed-off-by: Venkata Prasad Potturu <[email protected]> Reviewed-by: Matthias Kaehlcke <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-04-23pinctrl: qcom: Update lpi pin group custiom functions with framework generic ↵Srinivasa Rao Mandadapu1-0/+1
functions Update custom pin group structure members with framework generic group_desc structure and replace the driver's custom pinctrl_ops with framework provided generic pin control group functions to avoid redundant code written in lpass lpi driver. Signed-off-by: Srinivasa Rao Mandadapu <[email protected]> Co-developed-by: Venkata Prasad Potturu <[email protected]> Signed-off-by: Venkata Prasad Potturu <[email protected]> Reviewed-by: Matthias Kaehlcke <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: qcom: Introduce sc8280xp TLMM driverBjorn Andersson1-0/+9
The SC8280XP comes, like all other Qualcomm platforms, with a TLMM block, so add a driver for it. Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-12-09pinctrl: qcom: Add SM8450 pinctrl driverVinod Koul1-0/+9
This adds pincontrol driver for tlmm block found in SM8450 SoC This patch is based on initial code downstream by Elliot Berman <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-11-27Merge tag 'v5.16-rc2' into develLinus Walleij1-0/+2
Linux 5.16-rc2 is needed because nonurgent fixes headed for next are strongly textually dependent on a fix that was applied for rc2. Signed-off-by: Linus Walleij <[email protected]>
2021-11-21pinctrl: qcom: Add SDX65 pincontrol driverVamsi Krishna Lanka1-0/+9
Add initial Qualcomm SDX65 pinctrl driver to support pin configuration with pinctrl framework for SDX65 SoC. Signed-off-by: Vamsi Krishna Lanka <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/13acb3cb36349487dee9745ab040d8f1344d2096.1637048107.git.quic_vamslank@quicinc.com Signed-off-by: Linus Walleij <[email protected]>
2021-11-16pinctrl: qcom: fix unmet dependencies on GPIOLIB for GPIOLIB_IRQCHIPJulian Braha1-0/+2
When PINCTRL_QCOM_SPMI_PMIC or PINCTRL_QCOM_SSBI_PMIC is selected, and GPIOLIB is not selected, Kbuild gives the following warnings: WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP Depends on [n]: GPIOLIB [=n] Selected by [y]: - PINCTRL_QCOM_SPMI_PMIC [=y] && PINCTRL [=y] && (ARCH_QCOM [=n] || COMPILE_TEST [=y]) && OF [=y] && SPMI [=y] WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP Depends on [n]: GPIOLIB [=n] Selected by [y]: - PINCTRL_QCOM_SSBI_PMIC [=y] && PINCTRL [=y] && (ARCH_QCOM [=n] || COMPILE_TEST [=y]) && OF [=y] This is because these config options enable GPIOLIB_IRQCHIP without selecting or depending on GPIOLIB, despite GPIOLIB_IRQCHIP depending on GPIOLIB. These unmet dependency bugs were detected by Kismet, a static analysis tool for Kconfig. Please advise if this is not the appropriate solution. Signed-off-by: Julian Braha <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-11-05Merge tag 'pinctrl-v5.16-1' of ↵Linus Torvalds1-0/+17
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "The most interesting aspect is that we now have initial support for the Apple pin controller as used in the M1 laptops and the iPhones which is a step forward for using Linux efficiently on this Apple silicon. Core changes: - Add infrastructure for per-parent interrupt data to support the Apple pin controller. New drivers: - New combined pin control and GPIO driver for the Apple SoC. This is used in all modern Apple silicon such as the M1 laptops but also in at least recent iPhone variants. - New subdriver for the Qualcomm SM6350 - New subdriver for the Qualcomm QCM2290 - New subdriver for the Qualcomm PM6350 - New subdriver for the Uniphier NX1 - New subdriver for the Samsung ExynosAutoV9 - New subdriver for the Mediatek MT7986 - New subdriver for the nVidia Tegra194 Improvements: - Improve power management in the Mediatek driver. - Improvements to the Renesas internal consistency checker. - Convert the Rockchip pin control device tree bindings to YAML. - Finally convert the Qualcomm PMIC SSBI and SPMI MPP GPIO driver to use hierarchical interrupts. - Convert the Qualcomm PMIC MPP device tree bindings to YAML" * tag 'pinctrl-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (55 commits) pinctrl: add pinctrl/GPIO driver for Apple SoCs dt-bindings: pinctrl: Add apple,npins property to apple,pinctrl dt-bindings: pinctrl: add #interrupt-cells to apple,pinctrl gpio: Allow per-parent interrupt data pinctrl: tegra: Fix warnings and error pinctrl: intel: Kconfig: Add configuration menu to Intel pin control pinctrl: tegra: Use correct offset for pin group pinctrl: core: fix possible memory leak in pinctrl_enable() pinctrl: bcm2835: Allow building driver as a module pinctrl: equilibrium: Fix function addition in multiple groups pinctrl: tegra: Add pinmux support for Tegra194 pinctrl: tegra: include lpdr pin properties pinctrl: mediatek: add support for MT7986 SoC dt-bindings: pinctrl: update bindings for MT7986 SoC pinctrl: microchip sgpio: use reset driver dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add reset binding dt-bindings: pinctrl: qcom,pmic-mpp: switch to #interrupt-cells pinctrl: qcom: spmi-mpp: add support for hierarchical IRQ chip pinctrl: qcom: spmi-mpp: hardcode IRQ counts pinctrl: qcom: ssbi-mpp: add support for hierarchical IRQ chip ...
2021-10-07qcom_scm: hide Kconfig symbolArnd Bergmann1-1/+2
Now that SCM can be a loadable module, we have to add another dependency to avoid link failures when ipa or adreno-gpu are built-in: aarch64-linux-ld: drivers/net/ipa/ipa_main.o: in function `ipa_probe': ipa_main.c:(.text+0xfc4): undefined reference to `qcom_scm_is_available' ld.lld: error: undefined symbol: qcom_scm_is_available >>> referenced by adreno_gpu.c >>> gpu/drm/msm/adreno/adreno_gpu.o:(adreno_zap_shader_load) in archive drivers/built-in.a This can happen when CONFIG_ARCH_QCOM is disabled and we don't select QCOM_MDT_LOADER, but some other module selects QCOM_SCM. Ideally we'd use a similar dependency here to what we have for QCOM_RPROC_COMMON, but that causes dependency loops from other things selecting QCOM_SCM. This appears to be an endless problem, so try something different this time: - CONFIG_QCOM_SCM becomes a hidden symbol that nothing 'depends on' but that is simply selected by all of its users - All the stubs in include/linux/qcom_scm.h can go away - arm-smccc.h needs to provide a stub for __arm_smccc_smc() to allow compile-testing QCOM_SCM on all architectures. - To avoid a circular dependency chain involving RESET_CONTROLLER and PINCTRL_SUNXI, drop the 'select RESET_CONTROLLER' statement. According to my testing this still builds fine, and the QCOM platform selects this symbol already. Acked-by: Kalle Valo <[email protected]> Acked-by: Alex Elder <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2021-09-23pinctrl: qcom: Add QCM2290 pinctrl driverShawn Guo1-0/+8
It's a porting of pinctrl-scuba driver from CAF msm-4.19 kernel. The egpio and wake bits are removed. Signed-off-by: Shawn Guo <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-09-23pinctrl: qcom: Add SM6350 pinctrl driverKonrad Dybcio1-0/+9
This adds pincontrol driver for tlmm block found in SM6350 SoC This patch is based on downstream copyleft code. Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-09-02Merge tag 'pinctrl-v5.15-1' of ↵Linus Torvalds1-0/+17
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.15 kernel cycle, no core changes at all this time, just driver work! New drivers: - New subdriver for Intel Keem Bay (an ARM-based SoC) - New subdriver for Qualcomm MDM9607 and SM6115 - New subdriver for ST Microelectronics STM32MP135 - New subdriver for Freescale i.MX8ULP ("Ultra Low Power") - New subdriver for Ingenic X2100 - Support for Qualcomm PMC8180, PMC8180C, SA8155p-adp PMIC GPIO - Support Samsung Exynos850 - Support Renesas RZ/G2L Enhancements: - A major refactoring of the Rockchip driver, breaking part of it out to a separate GPIO driver in drivers/gpio - Pin bias support on Renesas r8a77995 - Add SCI pins support to Ingenic JZ4755 and JZ4760 - Mediatek device tree bindings converted to YAML" * tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (53 commits) pinctrl: renesas: Add RZ/G2L pin and gpio controller driver pinctrl: samsung: Add Exynos850 SoC specific data dt-bindings: pinctrl: samsung: Add Exynos850 doc MAINTAINERS: Add maintainers for amd-pinctrl driver pinctrl: Add Intel Keem Bay pinctrl driver dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver pinctrl: zynqmp: Drop pinctrl_unregister for devm_ registered device dt-bindings: pinctrl: qcom-pmic-gpio: Remove the interrupts property dt-bindings: pinctrl: qcom-pmic-gpio: Convert qcom pmic gpio bindings to YAML dt-bindings: pinctrl: mt8195: Use real world values for drive-strength arguments dt-bindings: mediatek: convert pinctrl to yaml arm: dts: mt8183: Move pinfunc to include/dt-bindings/pinctrl arm: dts: mt8135: Move pinfunc to include/dt-bindings/pinctrl pinctrl: ingenic: Add .max_register in regmap_config pinctrl: ingenic: Fix bias config for X2000(E) pinctrl: ingenic: Fix incorrect pull up/down info pinctrl: Ingenic: Add pinctrl driver for X2100. dt-bindings: pinctrl: Add bindings for Ingenic X2100. pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760. pinctrl: Ingenic: Improve the code. ...
2021-07-31drivers: qcom: pinctrl: Add pinctrl driver for sm6115Iskren Chernev1-0/+9
Based on CAF implementation with egpio/wake_reg support removed. Similar function names were merged to reduce total number of functions. Signed-off-by: Iskren Chernev <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-07-23pinctrl: qcom: Add MDM9607 pinctrl driverKonrad Dybcio1-0/+8
Add a pinctrl driver to allow for managing SoC pins. Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-07-23pinctrl: qcom: fix GPIOLIB dependenciesArnd Bergmann1-32/+31
Enabling the PINCTRL_SM8350 symbol without GPIOLIB or SCM causes a build failure: WARNING: unmet direct dependencies detected for PINCTRL_MSM Depends on [m]: PINCTRL [=y] && (ARCH_QCOM [=y] || COMPILE_TEST [=y]) && GPIOLIB [=y] && (QCOM_SCM [=m] || !QCOM_SCM [=m]) Selected by [y]: - PINCTRL_SM8350 [=y] && PINCTRL [=y] && (ARCH_QCOM [=y] || COMPILE_TEST [=y]) && GPIOLIB [=y] && OF [=y] aarch64-linux-ld: drivers/pinctrl/qcom/pinctrl-msm.o: in function `msm_gpio_irq_set_type': pinctrl-msm.c:(.text.msm_gpio_irq_set_type+0x1c8): undefined reference to `qcom_scm_io_readl' The main problem here is the 'select PINCTRL_MSM', which needs to be a 'depends on' as it is for all the other front-ends. As the GPIOLIB dependency is now implied by that, symbol, remove the duplicate dependencies in the process. Fixes: d5d348a3271f ("pinctrl: qcom: Add SM8350 pinctrl driver") Fixes: 376f9e34c10f ("drivers: pinctrl: qcom: fix Kconfig dependency on GPIOLIB") Signed-off-by: Arnd Bergmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-07-01Merge tag 'pinctrl-v5.14-1' of ↵Linus Torvalds1-0/+9
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.14 kernel. Not so much going on. No core changes, just drivers. The most interesting would be that MIPS Ralink is migrating to pin control and we have some bindings but not yet code for the Apple M1 pin controller. New drivers: - Last merge window we created a driver for the Ralink RT2880. We are now moving the Ralink SoC pin control drivers out of the MIPS architecture code and into the pin control subsystem. This concerns RT288X, MT7620, RT305X, RT3883 and MT7621. - Qualcomm SM6125 SoC pin control driver. - Qualcomm spmi-gpio support for PM7325. - Qualcomm spmi-mpp also handles PMI8994 (just a compatible string) - Mediatek MT8365 SoC pin controller. - New device HID for the AMD GPIO controller. Improvements: - Pin bias config support for a slew of Renesas pin controllers. - Incremental improvements and non-urgent bug fixes to the Renesas SoC drivers. - Implement irq_set_wake on the AMD pin controller so we can wake up from external pin events. Misc: - Devicetree bindings for the Apple M1 pin controller, we will probably see a proper driver for this soon as well" * tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (54 commits) pinctrl: ralink: rt305x: add missing include pinctrl: stm32: check for IRQ MUX validity during alloc() pinctrl: zynqmp: some code cleanups drivers: qcom: pinctrl: Add pinctrl driver for sm6125 dt-bindings: pinctrl: qcom: sm6125: Document SM6125 pinctrl driver dt-bindings: pinctrl: mcp23s08: add documentation for reset-gpios pinctrl: mcp23s08: Add optional reset GPIO pinctrl: mediatek: fix mode encoding pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq() pinctrl: bcm: Constify static pinmux_ops pinctrl: bcm: Constify static pinctrl_ops pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file pinctrl: ralink: move ralink architecture pinmux header into the driver pinctrl: single: config: enable the pin's input pinctrl: mtk: Fix mt8365 Kconfig dependency pinctrl: mcp23s08: fix race condition in irq handler ...
2021-06-18drivers: qcom: pinctrl: Add pinctrl driver for sm6125Martin Botka1-0/+9
This patch adds pinctrl driver for sm6125. Signed-off-by: Martin Botka <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-06-09pinctrl: qcom: Make it possible to select SC8180x TLMMBjorn Andersson1-1/+1
It's currently not possible to select the SC8180x TLMM driver, due to it selecting PINCTRL_MSM, rather than depending on the same. Fix this. Fixes: 97423113ec4b ("pinctrl: qcom: Add sc8180x TLMM driver") Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-04-14drivers: pinctrl: qcom: fix Kconfig dependency on GPIOLIBJulian Braha1-1/+1
When PINCTRL_MSM is enabled, and GPIOLIB is disabled, Kbuild gives the following warning: WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP Depends on [n]: GPIOLIB [=n] Selected by [y]: - PINCTRL_MSM [=y] && PINCTRL [=y] && (ARCH_QCOM || COMPILE_TEST [=y]) This is because PINCTRL_MSM selects GPIOLIB_IRQCHIP, without selecting or depending on GPIOLIB, despite GPIOLIB_IRQCHIP depending on GPIOLIB. Having PINCTRL_MSM select GPIOLIB will cause a recursive dependency error. Signed-off-by: Julian Braha <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-03-15pinctrl: qcom: sc8180x: add ACPI probe supportShawn Guo1-1/+1
It adds ACPI probe support for pinctrl-sc8180x driver. We have one problem with ACPI table, i.e. GIO0 (TLMM) block has one single memory resource to cover 3 tiles defined by SC8180X. To follow the hardware layout of 3 tiles which is already supported DT probe, it adds one function to replace the original single memory resource with 3 named ones for tiles. With that, We can map memory for ACPI in the same way as DT. Signed-off-by: Shawn Guo <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12pinctrl: qcom: Add sc8180x TLMM driverBjorn Andersson1-0/+9
Add pinctrl driver for the sc8180x TLMM block. A noteworthy difference from previous TLMM blocks is that the registers for GPIO 177 through 189 are for some reason offset from the typical layout. Other than that the driver is same old... Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2021-02-12pinctrl: qcom: Add SM8350 pinctrl driverVinod Koul1-0/+9
This adds pincontrol driver for tlmm block found in SM8350 SoC This patch is based on initial code downstream by Raghavendra. Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
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